1. The concept of
SPI SPI is called Serial Peripheral Interface, which is translated as Serial Peripheral Interface in Chinese. SPI is a high-speed, full-duplex, and synchronous communication bus. It only occupies four pins on the chip, namely SCLK (clock), MISO (master data in), MOSI (master data out), CS (chip select).
2. The communication protocol
SPI communication is a master-slave structure, which can be a master-slave structure, or a master-slave structure. When the host needs to send a message to the slave, it first pulls CS low, and then transmits the clock and data at the same time. It should also be noted here that different devices have different clock polarity configurations (CPOL), different clock polarity configurations, its idle conditions and read and write conditions are different. As shown in the figure below: 
when CPOL=0 and SCLK=0, it is in the idle state;
when CPOL=1 and SCLK=1, it is in the idle state;
Ordinary serial communication must transmit at least 8 bits per transmission, but SPI can transmit bit by bit, because Master controls SCLK, CLK can be turned off at any time. The following two pictures briefly show the process of data transmission. Assume that the master SBuffer=0XAA, and the slave SBuffer=0X55;
It is assumed here that CPOL=0 is configured, that is, the master sends and receives from the machine at the rising edge, and the slave sends the host to receive at the falling edge. SPI works in a full-duplex state. After 8 clocks, the data in the SBuff of the master and slave are converted to each other.
3. Disadvantages of SPI: No flow control or feedback mechanism.
Getting to know eSPI
1. Introduction to
LPC LPC (Low Pin Count) communication bus, Intel announced on September 29, 1997. , Is a communication bus that can replace the ISA bus developed by IBM.
Although the transmission speed of LPC is slow, it is particularly suitable for the realization of communication between slow peripherals and PCH. It is commonly used for Supper IO/EC/BMC/80Port Debug Card, SI/O is for Desktop flatform, EC is for Notebook flatform, and BMC is for Server flatform.
Disadvantages of LPC:
1) The LPC bus regulation defines 7 necessary signals and 6 optional signals, which requires a total of 13 pins of the processor, plus a large number of sideband signals between the chipset and EC/BMC/SIO. The system architecture with tight pin resources urgently needs a bus communication method that occupies fewer hardware pins;
2) The existing implementations of LPC are based on 3.3V IO level, which is not conducive to low-power design;
3) Fixed LPC bus clock At 33MHz, the bus data throughput can only reach 133Mbps, which has become the data bottleneck of the system.
2. The concept of eSPI
In 2016, Intel introduced a new generation of bus interface specification eSPI (Enhanced Serial Peripheral). The
eSPI bus draws on and multiplexes the electrical clock specification of the SPI bus, but uses a new definition at the protocol layer, so both Whether it is from the function or from the application is completely different. Please don't confuse it simply because the names are similar. In addition to being fully compatible with the functions and functions of the LPC bus, the eSPI bus also converts OOB (out of band) SMBUS and SideBand GPIO to the In Band Message that can be transmitted on the eSPI Bus. In addition, it can also communicate with the chipset in real time. Share flash. The connection diagram of eSPI BUS and Chipset is as follows: