3.Bus

bus

1. The basic concept of the bus

1.1 Why use a bus

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1.2 What is a bus

Bus: Bus

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1.3 Transmission of information on the bus

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Parallel: short transmission distance

Serial: Long transmission distance

Serial fast

1.4 Example of a computer with a bus structure

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**Question: ** Only one pair of components can use the bus at any time, and the bus becomes the bottleneck of the system

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Problem: Information transfer occurs between peripherals and main memory, and the CPU is used as the medium, and the CPU is busy

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Problem: At present, the system bus and storage bus cannot work at the same time.

2. Classification of the bus

2.1 Divided according to the location of the bus

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USB, network port: serial

3. Bus characteristics and performance indicators

3.1 Bus physical realization

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3.2 Bus characteristics

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3.3 Performance indicators of the bus

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3.4 Bus standard

PCI

To understanding

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4. Bus structure

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Channel: usually written by the operating system

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There can be multiple high-speed peripherals

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所谓三线：I/O总线、主存总线和DMA总线

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4.1 Example of bus structure

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5. Bus control

5.1 Arbitration control of the bus

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5.1.1 Chain query mode

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Advantages: simple structure, simple addition and deletion of equipment, simple priority algorithm, easy to achieve reliability design

Disadvantages: sensitive to circuit failure, especially BG line, slow speed

5.1.2 Counter timing query mode

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Advantages: flexible priority order

Disadvantages: slow

5.1.3 Independent request method

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Advantages: more flexible priority order

Disadvantages: Need a lot of wires

5.2 Bus communication control

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Also withdraw relevant information from the module

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5.2.1 Synchronous data input

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Fixed-width and fixed-distance clock control

5.2.2 Synchronous data output

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一般应用在总线长度比较短 、各个模块存储时间比较一致

5.3 Asynchronous communication

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Asynchronous communication uses handshake signals

5.4 Semi-synchronous communication (combination of synchronous and asynchronous)

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5.4.1 Semi-synchronous communication timing taking input data as an example

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wait signal: if the data is not ready from the module, insert a wait signal

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5.5 Summary

上述三种通信的共同点

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5.6 Separate communication

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That is to change from the module to the main module in the sub-cycle

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5.5 Summary

上述三种通信的共同点

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5.6 Separate communication

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That is to change from the module to the main module in the sub-cycle

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