@ FPGA convolution realizes folding, moore, approximate addition
FPGA convolution principle
The principle of convolution is not much to say. The specifics are all under Baidu. The overall idea here is serial input and parallel calculation. The principle is to cache the image for three lines, then extract the three rightmost lines of each line and multiply it by the coefficient of the convolution kernel, and then accumulate the nine results. The matrix is passed in in the form of data stream, one pixel by one into the folded three-layer buf, the output matrix is also passed out according to the column, and enters the multiplication module. The data after 9 multiplications enters the addition tree, and the bottom layer of the addition tree is called It is the module that calls the approximate addition, and when the output result is valid, res-valid will be pulled high. Because it is a convolution of the valid type, it is written here that there is no edge padding, so the entering image matrix is 32 32 type. each sliding window is a convolution calculation value, and the control state machine and the read data conversion, the final matrix obtained 30 30 type
# realization diagram