Three, the use of Makefile
1. Why do you need Makefile?
After writing the program, if only one source file (such as .h file) is changed, then it is impossible to recompile all source files through a series of commands, and sometimes there are more source files that have been changed. Finally, forget to compile some source files. The make tool can solve the above problems, it will recompile all source files affected by the changes when necessary. The Makefile tells make how to compile and link into a program. The benefit of Makefile is-"automatic compilation", once it is written, only one make command is needed, and the entire project is completely automatically compiled, which greatly improves the efficiency of software development.
Makefile files are generally placed in the same directory as the other source files of the project.
2. Simple rules of Makefile:
A simple Makefile file contains a series of "rules", the style is as follows:
Target : dependent (prerequiries) // target program or file dependent on : dependent file
<tab>Command (command) //If the "dependent file" is newer than the "target file" (that is, changed), then execute the "command" to regenerate the "target file"
Two commands are executed conditions : dependent files than the target file new or target document also did not generate .
Commands are actions executed by Make. A rule can contain several commands, and each command occupies one line. Note: Each command line must be preceded by a Tab character, that is, the first character of the command line is Tab. This is where accidents are easy to make mistakes.
3. First introduce the 2 functions of Makefile
A. $(foreach var,list,text)
Simply put, it is for each var in list, change it to text.
For each element in the list, take it out and assign it to var, and then change var to the form described by text.
example:
objs: = to the bo
dep_files := $(foreach f, $(objs), .$(f).d) // final dep_files := .aod .bod
B. $(wildcard pattern)
Whether the files listed in the pattern exist, list all existing files.
example:
src_files := $( wildcard *.c) // Finally, all .c files in the current directory are listed in src_files
4. When using the make command, it will first search for a file named Makefile in the current directory, then execute the commands in the Makefile, and display the executed commands on the terminal, such as:
book@100ask：~/04_test_Makefile$ make
gcc -c -o main.o main.c
gcc -c -o sub.o sub.c
gcc -o test main.o sub.o
If the target program/file does not need to be changed, it will prompt that the target program is up to date:
book@100ask：~/04_test_Makefile$ make
make：'test' is up to date.
5. When creating a Makefile file, select the file format as Makefile
6. The execution of the commands is sequential: if the commands of the Makefile file are as follows:
test : main.o sub.o
gcc -o test main.o sub.omain.o : main.c
gcc -c -o main.o main.csub.o : sub.c
gcc -c -o sub.o sub.c
The first target file test depends on main.o and sub.o, because main.o does not exist, skip to the second command, so execute gcc -c -o main.o main.c first; then go back to the first Line, it is found that sub.o does not exist, so skip to the third paragraph and execute gcc -c -o sub.o sub.c; back to the first line, the two dependent files are present, and the target file is generated if the conditions are met test
7. make clean: Only execute the relevant commands of the target file clean in the Makefile.
8. $@ means all target files, $^ means all dependent files, and $< means the first dependent file
%.o ：%.c
gcc -c -o $@ $^
9. When a target file has two dependent files, one of which has a command and the other has no command, then the two dependent files will be merged together. Changing the dependent file without a command will also trigger another dependent file command.
However, a blank line is required below the dependent file without a command and the blank line cannot have the Tab key.
10. The effect you want to achieve: When you modify the source file or header file, just use the make command to recompile the involved files, and you can regenerate the APP: Please see section 4-3-1 (not understand)
①Why make clean works Repeated use? Isn't clean a program like test? If clean exists, why can it be generated repeatedly?
②Why change to the file format of .main.d?
③What is the usage of objs := main.o sub.o?
④Why use the form of ${objs} when using objs?
11. How to use general Makefile:
(1) Put the top-level Makefile, Makefile.build into the top-level directory of the program and
create a blank Makefile in the respective sub-directories
(2)
Steps to determine which source files to compile :
(1) Modify and add obj-y of Makefile in the top-level directory as needed
(2) Add obj-y to the blank Makefile in each subdirectory
The description of obj-y:
obj-y += xxx.o
obj-y += yyy/
①This means to compile xxx.c in the current directory (compile the .c file to obtain the .o file) and the yyy subdirectory ( The Makefile in the yyy directory will specify the files and subdirectories that need to be compiled in the directory)
②The slash / which means yyy is a subdirectory / cannot be omitted
(3)
Steps to determine compile options and link options :
(1) Modify the CFLAGS of the top directory Makefile , which is a compile option that must be used when compiling all .c files;
there is such a paragraph in the top Makefile:
CFLAGS += -I $(shell pwd)/include
Because all the header files in a project file are placed in the include directory, this paragraph means: when compiling all .c files, it will find the include directory (the header file in the file) under the file.
(2) Modify the LDFLAGS of the top-level directory Makefile , This is the link option when linking the last application;
LDFLAGS can specify the location of the library and the name of the library when linking:
LDFLAGS := -L dir -labc
-L is the location of the specified library is the dir directory under the current location, -l (lowercase L) specifies the name of the library as abc
(3) Set other compilation options (optional) and
modify the Makefiles in their respective subdirectories:
"EXTRA_CFLAGS", which sets additional compilation options for all files in the current directory (excluding subdirectories under it). You can leave it alone
. CFLAGS_xxx.o", it sets its own compilation options for xxx.c in the current directory, can it not be set
(4) Which compiler is used?
Modify the CROSS_COMPILE in the first line of the top-level directory Makefile to specify the prefix of the tool chain (such as arm-linux-).
If it is compiled under gcc, no assignment is performed.
(5) Determine the name of the application:
modify the TARGET of the top-level directory Makefile , This is used to specify the name of the compiled program, such as:
TARGET := test
(6) Execute "make" to compile, execute "make clean" to clean up, and execute "make distclean" to clean up completely
(7) When the compilation is successful, it will prompt "xxx has been built!"
(8) The source code location of general Makefile: [Part 4] Basic knowledge of embedded Linux application development/source/05_general_Makefile
12. Analysis of general Makefile: Section 4-3-3, skipped
Analysis of the meaning of the commands in the Makefile and the design ideas of the Makefile,
please refer to Section 3.0.3 and Section 3.0.3 of Chapter 4 "Basic Knowledge of Embedded Linux Application Development" Section 3.1