In semiconductor manufacturing, Moore’s Law is always followed, so the size of integrated circuits continues to decrease, so the channel length of the MOSFET is shortened accordingly, which leads to the distance between S and D (source and drain) in the MOSFET. Shorter and shorter, so the gate's ability to control the channel becomes worse, which means that the gate voltage pinch off the channel becomes more difficult, so subthreshold leakage (subthreshold leakage) phenomenon, that is, short The channel effect (short-channel effect) is more likely to occur.
Professor Hu Zhengming gave a very easy to understand example: when a water pipe is very long, it can be easily blocked (or stepped on) with a stone, but when it is very short, This stone may not be able to block the water pipe, because it may not fit, which corresponds to the above paragraph, the shorter the channel, the more difficult it is to block the current (to prevent leakage)
Influencing factors of short channel effect
There are the following five types. Simply put, the channel is short and easy to leak.
(1) The increase in electric field caused by the failure of the power supply voltage to scale down;
(2) The built-in potential can neither be scaled down nor ignored;
(3) The source and drain junction depth cannot and cannot be reduced proportionally;
(4) An increase in the substrate doping concentration causes a decrease in carrier mobility;
(5) The sub-threshold slope cannot be scaled down
In order to reduce the impact of the short channel effect, new methods such as strained silicon technology, high-K dielectric oxide layer, metal gate, and SOI have been proposed to improve device performance. However, in the process node below 28 nm, the effective control of the gate to the channel in the planar MOSFET device structure is facing severe challenges, while the innovative three-dimensional device structure, such as the Fin FET structure, has more effective gate control and can obtain more Excellent device performance.
There is a little question here: Why can the increase of channel contact surface alleviate the occurrence of short channels? This is the proof of the experimental part in the original FinFET process below. My current understanding is that it can make the grid easier to pinch off the current.
FinFET process
The concept of FinFET is originally derived from the idea of a dual-gate MOS transistor, which enhances the control of the conduction channel by increasing the contact area between the gate and the channel
Due to the growth of the channel contact surface, the short channel effect can be alleviated to a certain extent, so that the chip manufacturing process can continue to be explored.
Samsung has an improved version- GAA (gate all around) , which is about this long. It can be clearly seen that the idea is basically the same, and the channel area calculation has changed from three sides to four sides.
There are other SOI Fin FETs, but I haven’t read it carefully yet, I don’t understand, so I won’t talk about it for the time being. I guess it should be another way to increase the channel area~, refer to: Overview of FinFET Device Structure Development
to sum up
The channel is short-short channel effect-new materials, FinFET technology, etc. alleviation (k value (dielectric constant) and area)
Just as teacher Hu Weiwu predicted in the book Architecture Fundamentals: Moore's Law is coming to an end around 2020 (this is true, but I don’t know how TSMC’s 3nm is done), it is difficult to shrink the size of transistors (refer to Xiaolong 888 power consumption rollover event), if it can be improved, it is most likely to be inventions such as new materials
