A 555 oscillator circuit and its explanation
555 working voltage is 5-18V, 555 chip pin diagram:
internal structure: according to the voltage divider, comparator, RS trigger, output stage, discharge switch composed of several parts
RS trigger diagram
rs trigger consists of two NAND gates Positive and negative feedback formation.
When R=0 and S=1 , assuming that the output of Q is high, one input terminal of the NAND gate G2 is high and the bar R=0, so Q is not high, Q is not the input terminal of the NAND gate G1 and S= 1. So the Q output is low and the hypothesis contradicts. On the contrary, if the Q output is low, the deduced result is consistent with the hypothesis.
When R=1 and S=0 , assuming that the output of Q is high, one input terminal of the NAND gate G2 is high and R=1, so Q is not low, and Q is the input terminal of the NAND gate G1 and the bar S= 1, so the Q output is high in line with the hypothesis, and vice versa, the hypothesis contradicts.
When R=1 and S=1 , the Q output is Qn, which means to keep the previous state unchanged. This is a dynamic change. It depends on the previous state to see whether the Q output is high or low. Separate judgment R=1, S=1, Q output high or low is established, but it keeps the last state unchanged because the basic RS flip-flop has a memory function, it keeps the last state and does not want to change.
When R=0 and S=0 , the output of Q is high, but the state of Q on the truth table is uncertain. When R and S change from 0 to 1 at the same time, the state of Q is uncertain. Separately judge R=1, S When =1, Q output is high or low. Why is he uncertain? Because in this state where R and S are both zero, both Q and Q will output high. When R and S are both 1, Q and Q must be zero. However, we don’t know whether Q is or Q. Whoever changes first does not know the transmission speed of the two NAND gates, so it is not sure whether the Q output is high or low.
The following figure is its truth table :
Multivibrator circuit diagram
Charge period (output 1)
T1=0.7 (R1+R2) C2
discharge period (output 2)
T2=0.7R2C2
period
T=T1+T2=0.7 (R1+2R2) C2
duty cycle
q=T1 /T
The simulation is as follows:
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