The figure above shows an 8-core CPU computer system. Each CPU has a cache (a cache and register inside the CPU). There is also an interconnection module in the die, so that the two cores in the die can communicate with each other. The system interconnect module in the center of the figure allows four die to communicate with each other and connect the die to the main memory. Data is transmitted in the system in units of "cache lines", which correspond to a power-of-two byte block in memory, usually between 32 and 256 bytes in size. When the CPU reads a variable from memory to its register, it must first read the cache line containing the variable to the CPU cache. Similarly, when the CPU stores a value in a register into memory, it must not only read the cache line containing the value to the CPU cache, but also must ensure that no other CPU has a copy of the cache line.
For example, if CPU0 is performing a "compare and swap" (CAS) operation on a variable, and the cache line where the variable is located is in the cache of CPU7, the following simplified sequence of events will occur:
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CPU0 checks the local cache and no cache line is found.
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The request is forwarded to the interconnection module of CPU0 and CPU1, the local cache of CPU1 is checked, and no cache line is found.
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The request is forwarded to the system interconnection module, the other three die are checked, and it is learned that the cache line is held by the die where CPU6 and CPU7 are located.
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The request is forwarded to the interconnection module of CPU6 and CPU7, the caches of these two CPUs are checked, and the cache line is found in the cache of CPU7.
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CPU7 sends the cache line to its own interconnection module and refreshes the cache line in its own cache.
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The interconnection module of CPU6 and CPU7 sends the cache line to the system interconnection module.
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The system interconnection module sends the cache line to the interconnection module of CPU0 and CPU1.
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The interconnection module of CPU0 and CPU1 sends the cache line to the cache of CPU0.
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CPU0 can now perform CAS operations on variables in the cache