table of Contents
01. Introduction to JTAG
JTAG (JointTest Action Group) is an interface. A group called JTAG group was established for this interface, which was established in 1985. In 1990, IEEE felt that everything was in order, so it released IEEE Standard 1149.1-1990 and named it Standard Test Access Port and Boundary-Scan Architecture. This is the famous JTAG.
Do you know the three major functions of JTAG?
1. Downloader, that is, download software to FLASH.
2. DEBUG, like a doctor's stethoscope, can listen carefully to the inside of the chip.
3. Boundary scan, you can access the signal logic state inside the chip, and the state of the chip pins, etc.
JTAG has no standard interface definition at all, and even the definition varies from company to company. In ARM's "System and Interface Design Reference" document
Document download address:
Link: https://pan.baidu.com/s/13aQXOXR73_wiERz2kwN15w
Extraction code: xaaf
This document lists the different JTAG interfaces
The picture below, which we often see on the Internet, is the JTAG interface of SEGGER’s Jlink.
J-Link is a JTAG-based emulator launched by the German SEGGER company. Simply put, it is a JTAG protocol conversion box, that is, a small USB to JTAG conversion box, which is connected to the computer with the USB interface, and the jtag protocol is used inside the target board. It has completed a conversion from software to hardware.
At the same time, Jlink is also the most popular debugger in my opinion. According to the "System and Interface Design Reference", this ARM official JTAG20pin is not the same.
Here I hope everyone understands the relationship between ARM, Jlink, and JTAG.
The interface of ST-linkV2, which is also used frequently, can be seen from the above, which is also the interface defined by ST itself, as follows:
Ulink, CMSIS_DAP and other STM32 simulators are the same.
02, JTAG introduction
Boundary test:
For example, if you have two chips, there are many wires connected between the two chips. How to ensure that the connections between these wires are OK? With JTAG, it can control all IC pins. This is called chip boundary testing.
In the JTAG interface, there are four most commonly used signals, namely TCK/TMS/TDO/TDI. The JTAG interface can be used one-to-one, and can also form a one-to-many topology of a daisy chain. The two topologies are shown in the following figure. Multi-core chips have been connected in the form of a daisy chain inside the chip.
There are many ways to play the daisy chain of JTAG
CPU and FPGA manufacturers allow JTAG to be used for port debugging; FPGA manufacturers allow the FPGA to be configured through JTAG and use JTAG signals to access the FPGA core.
03, JTAG and SWD
SWD interface: Serial Debug (SerialWireDebug), should be regarded as a different debugging mode from JTAG, the most direct manifestation is in the debugging interface, compared with the 20 pins of JTAG, SWD only needs 4 (or 5) Pin.
VCC, SWDIO, SWCLK, GND (in some cases, the RESET pin is also added).
The difference between SWD and traditional debugging methods:
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SWD mode is more reliable than JTAG in high-speed mode. In the case of a large amount of data, the JTAG download program will fail, but the chance of SWD will be much smaller. The SWD mode can be used directly when the JTAG emulation mode is basically used, as long as your emulator supports it, so it is recommended that you use this mode.
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When the CPU's GPIO is not enough, you can use SWD emulation, this mode supports fewer pins.
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SWD mode is recommended when the size of the hardware PCB is limited. It requires less pins, and of course, the PCB space required is small. You can choose a small 2.54 pitch 5-pin terminal as an emulation interface.
JTAG mode and SWD mode of Jlink debugger in Keil environment
JTAG mode and SWD mode of Jlink debugger in IAR environment
Jlink's JTAG mode and SWD mode comparison chart
JTAG pin description
SWD pin description
04. About the Vref pin
We mentioned above that the Vref pin belongs to the power domain of the IO interface. The purpose is to make the logic level of the chip consistent with the logic level of the debugger to avoid logic errors and even damage the equipment.
There is a jumper cap for Vref on Jlink.
Three headers: ① is NC, ② is Vref, which is connected to pin 1 of the output, ③ is 3.3V
If you want Jlink's 1 pin Vref to output 3.3V, just short ② and ③ directly.
05. About the TRST pin
The TRST pin in the JTAG definition is used to reset the TAP controller. In STM32 series microcontrollers, there is no TRST pin, and the name is NJTRST.
Take STM32F207 as an example, the description of NJTRST pin in JTAG and SWD mode.
SWJI/O pin availability of STM32F207
06, RESET pin function
In some STM32 products, the 4-wire SWD mode is used during simulation. The release version usually sets the JTAG port to ordinary IO, or because the pins are not enough, it is used for other purposes in the release version. We are debugging the release version, because JTAG mode is disabled, there is no way to emulate.
At this time, the most commonly used method is to pull up the BOOT0 pin, enter the MainFlash memory mode, and perform debug simulation.
Compared with the official development board of STM32, we did not lead out the RST pin when using SWD mode. Of course, there is also the SWO signal that belongs to SWD. This is for monitoring and also very useful. Both of these signals can be connected to the emulator.
Control on the board:
The emulator has an UnderReset method. Therefore, when the emulator needs to emulate, it will send the RST signal to the MCU to make the MCU in RST, or emulate after reset, the code has not been executed to the state of prohibiting JTAG, so it can be directly emulated . Of course, you can also actively reset the power supply, or you can leave the original JTAG prohibited state. You can also pull up the boot0 pin.
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