AD7606 read logic, parallel 16-bit mode

Initial state: CONVSTAB is high, CS is high, RESET is low, RD is high.
Start to
reset
CONVSTAB conversion signal.
Wait for busy
CS to pull low and
RD pull low.
Wait for FRSDATA==high level.
Read the value of V1 channel and
RD pull high
for(i=0; i<7;i++)
{ delay 20ns RD pull low, delay 10ns read the value of Vi channel delay 20ns RD pull high } RD pull high CS pull high CONVSTAB pull high