Quartus Prime basic usage method and simulation errors

Preface

Several design methods commonly used by Quartus, circuit diagrams, direct use of language or a combination of the two methods, this article briefly introduces three methods and possible problems and two simulation methods.

1. Circuit diagram

This method is suitable for gate-level circuits to build simple circuit modules.

1. First create a new Block Diagram/Schematic File
   2. Open the newly created .bdf file. Double-click the blank space to add the required gate units and larger circuit units.
   3. After the circuit is successfully built, just compile it.

2. VHDL/Verilog HDL language

1. Same as above, create a new VHDL/Verilog HDL file
2. Write the relevant code and compile it

3. Bottom-up (language + schematic diagram)

1. Note: The name of the top-level entity needs to be the same as the name of bdf
2. Use VHDL/Verilog HDL language to write different circuit units and generate symbol files.
3. Create a new bdf file, double-click, and you can find the circuit unit just created in the project.
   4. Compile after wiring the circuit unit.

4. Two simulation methods

1. Directly use the simulation in Quartus

• Create University Program VWF file
  

• Open the created wave file, double-click in the blank space, and add the node you need to observe
  

• Click on node Finder, the circuit nodes can be displayed through the list
  

• Move the found node into the selected node and click OK to confirm
  

• Click OK to confirm
  

• Display Wave File
  

• Through the shortcut buttons in the menu bar, you can set to 0, set to 1, set the clock, select function simulation or timing simulation, and the simulation waveform appears.
  

• Possible errors
  1 File path error Error (199014): Vector source file F:/quartuslite/Waveform2.vwf specified with --testbench_vector_input_file option does not exist
  Error: Quartus Prime EDA Netlist Writer was unsuccessful. 1 error, 1 warning
  Error: Peak virtual memory: 4723 megabytes
  Error: Processing ended: Sun Oct 04 20:32:19 2020
  Error: Elapsed time: 00:00:02
  Error: Total CPU time (on all processors): 00:00:02
  Solution: Save vmf file, just save it in the default path. Or modify the path of the testbench file in the Simulation configuration in the vmf file
  

  2# ** Error (suppressible): (vsim-12110) The -novopt option has no effect on this product. -novopt option is now deprecated and will be removed in future releases.
  Error loading design
  

  Solution: delete -novop after vsim

2. Simulation using modelsim

• Add modelsim path, click tools->options, select modelsim path, be sure to choose modelsim or modelsim altera, in this path, remember the last "\", modelsim can be found in the path. Otherwise, it will report an error "Can't launch the ModelSim-Altera software". Modelsim altera is used in the picture below.
  

• Configure project, right click settings
  

• Add the testbench file, note that the Test bench name in the fifth step is the testbench file name, and the Top level module in test bench is the module name in the testbench file

• Just start RTL Simulation