Computer LD
What are the stages of a complete interruption process?
Answer: Including: interrupt request, interrupt arbitration, interrupt response, interrupt processing and return.
1. Assuming that a certain program P consists of a cycle consisting of 100 instructions, the cycle is executed 50 times in total, and it takes 20,000 clock cycles to execute program P in a system S, what is the CPI of system S when executing program P ?↵
Answer: A total of 100X50=5000 instructions are executed in 20000 clock cycles
CPI = 2000/5000 = 4
2. What does the accuracy and numerical range of floating-point number representation depend on? What is the relationship? ↵
Answer: The accuracy of floating-point numbers depends on the number of digits in the mantissa, and the value range depends on the number of digits in the order code.
When the total digits of floating-point numbers remain unchanged, the more the order code digits, the fewer the mantissa digits. That is to say, the larger the number range, the worse the accuracy (the number becomes sparse).
3. Draw a diagram of the components of the complement plus and minus operation
4. What is the "locality of program access"? Which level of the storage system adopts the principle of program access locality?
↵ Answer: The memory access is uneven when the program is executed. This is because the address distribution of instructions and data in the main memory is not random, but relatively clustered. ↵
The Cache-main memory level and main memory-auxiliary memory level of the storage system both use the principle of program access locality.
5. Suppose the main memory of a certain machine is 16MB, the Cache capacity is 16KB, and each word block is 32 bytes. Design a Cache organization of four-way group associative images, and draw the number of bits in each segment in the main memory address field.
Answer: 32 bytes per word block, 2 5 = 32, the address in the block is 5 bits; ↵
The Cache content is 16KB, 16K/32=512, then the Cache has a total of 512 blocks. Because it is connected in four groups, there are 512/4=128 groups, and the group number is 7 bits;
The main memory capacity is 16M, 2 24 = 16M, marked as 24-5-7 = 12 bits
| 12 | 7 | 5 |
|---|---|---|
| mark | Group No | Block address |
6. What are RISC and CISC? Try to compare the similarities and differences in several aspects, such as the number of instructions, instruction format, addressing mode, general-purpose register number, what logic is used, the compilation technology used, the degree of pipeline support, and reliability. Cite a typical architecture using RISC and CISC respectively.
Answer: RISC is a simplified instruction set computer, CISC complex instruction set computer. Compared with CISC, RISC has fewer instructions, instruction formats, and addressing modes, and general-purpose registersmany,useCombinatorial logic,useoptimizationCompiler technology, easy to achieve instruction pipeline. RISC is easy to design,Lower cost and higher reliability。
For example, the X86 architecture uses CISC, and both ARM and MIPS use RISC.
7. Suppose a machine can complete 120 operations in total. The CPU has 8 general registers, the main memory is 16K words, and the register-memory type instructions are used. If the instruction can directly access any address in the main memory, how many bits should the instruction word length take? Draw the instruction format.
answer:
Opcode: 7 bits
Register number: 3 bits;
Memory address code: 14 bits
Instruction word length=7+3+14=24 bits
| 7 | 3 | 14 |
|---|---|---|
| ON | R | A |
8. What is data hazard? How to solve data hazard? ↵
Answer: In the instruction pipeline, when the following instructions need to use the result of the previous instruction, the phenomenon that the result of the previous instruction has not yet produced is called data hazard.
The solutions are:
Method 1: Hardware blocking (stall);
Method 2: Software insert "NOP" instruction;
Method 3: Realize the read/write operation of the register file reasonably (cannot solve all data risks), write in the first half clock cycle, and read in the second half clock cycle. If the data written by the previous instruction in the same clock is exactly the data read by the subsequent instruction, No data hazard will occur;
Method 4: Forwarding (Forwarding or Bypassing bypass) technology;
Method 5: Compilation optimization: adjust the order of instructions (cannot solve all data hazards). ↵
9. What are the ways of centralized bus judgment? Which one is most sensitive to circuit failure? Which one has the fastest speed? ↵
Answer: The bus centralized ruling hasChain query、Counter timing query、Independent request methodThree kinds. Among them, the chain query is the most sensitive to circuit failures, and the independent request mode has the fastest ruling speed. ↵
10. What are the basic methods for data exchange between I/O devices and the host? In each method, is the data directly exchanged with the CPU?
Answer: There are three basic methods for data exchange between IO devices and the host:
Program query mode, interrupt mode, DMA mode.
Among them, the program query mode and interrupt mode peripheral teaching data are directly exchanged with the CPU, and the peripheral data and main memory are directly transferred in the DMA mode.
11. What are the commonly used data addressing methods?
Answer: Immediate addressing, direct addressing, implicit addressing, register addressing, register indirect addressing, indexed addressing, relative addressing, base addressing, etc.
12. The size of the main memory address space of a computer is 64KB, addressing in bytes, and it has been equipped with a ROM area of 0000H~7FFFH. If a 4KX4-bit RAM chip is used to form the rest of the RAM storage area, how many such are needed RAM chip? Write out the analysis process. ↵
Answer: Because the size of the main memory address space is 64KB, addressing by byte, the main memory address range is
0000H~FFFFH, of which 0000H~7FFFH is the ROM area, occupying 32KB, and the RAM area size is 64-32=32KB, so it needs The number of 4KX4-bit RAM chips is: 32KB/(4K X 4b)=16 pieces
13. The word length of a certain machine is 32 bits, the controller adopts the microprogram control method, the microinstruction word length is 32 bits, and the microinstruction format combining horizontal direct control and field coding control is adopted. There are 40 micro-commands in total, of which 9 micro-commands Command adopts direct control mode, 31 micro-commands adopt field coding control mode, forming a total of 4 mutually exclusive categories (each containing 7, 16, 3, and 5 micro-commands). There are 2 external conditions that can be tested. Design the specific format of the microinstruction, what is the control memory content? What is the difference between a microprogram controller and a hard-wired controller?↵
Answer: (1) The microinstruction format is as follows:
| 9 micro instructions | 7 micro instructions | 16 micro instructions | 3 micro instructions | 5 micro instructions | Discriminant field | Address field |
|---|---|---|---|---|---|---|
| 9 | 3 | 5 | 2 | 3 | 2 | 8 |
(2) The lower address field has 8 bits, and the control memory contains 2 8 = 256 units. ↵
14. A computer’s Cache has 16 blocks in total, using 2-way group connection mapping. Each main memory block is 32 bytes in size and is addressed by byte. What is the group number of the main memory block where the main memory number unit No. 129 should be loaded into the cache? The analysis process is given. (Cache start line 0, the answer is expressed in decimal)
answer:
Solution 1: Each word block has 32 bytes, so the address in the block is 5 bits;
The Cache has 16 blocks, using 2-way group connection mapping, a total of 8 groups, the group number is 3 bits, and the remaining high bits are marks.
The binary representation of number 129 is: 10000001
| mark | Group No | Block address |
|---|---|---|
| 0 | 100 | 00001 |
The group number is 100, which is the fourth group.
Solution 2: The block number of unit 129 is: 12932=4. The number of Cache groups is 162-=8 groups. The group number of the 4th block is: mod 8=4. That is in group 4.
15. The instruction format and addressing mode of a 16-bit machine are shown below. Assuming that the machine has 8 16-bit general-purpose registers, the operation code of the addition instruction ADD is 234H. Write the machine code of the following command statement (required to be expressed in hexadecimal):
ADD R7，R5
| 15 ， 8 | 7 ，4 | 3， 0 |
|---|---|---|
| on | D (destination register) | S (source register) |
ADD D,S
Answer: ADD machine code: 1000110100
R7 machine code: 111
R5 machine code: 101
Instruction sentence machine code 1000 110 100 111 101
Represent the bit in hexadecimal 8D3DH
16. In interrupt mode, can the peripheral request an interrupt at any time and get a response immediately?
Answer: In interrupt mode, the timing of the peripheral's interrupt request is determined by the interrupt logic in the peripheral interface and is not limited by the CPU. But when to respond to the interrupt is related to the process of the CPU executing instructions.
The CPU always inquires whether there is an interrupt request before an instruction is executed and the instruction is removed. If it is in the interrupt state and there is an unmasked interrupt request, it will respond after the execution of an instruction.
17. According to the different reasons that lead to the risk, what are the types of pipeline adventures? In the pipeline mode, is there any risk in the next set of instructions? Why? ↵
Ⅰ1 SUB R1,R2,R3;(R2 - R3) ->R1
Ⅰ2 ADD R4,R6,R1; (R1 + R6) ->R4
Answer: Pipeline adventure is divided into structure adventure, data adventure, and control adventure.
This set of instructions has data hazards.
The operation result of Ⅰ 1 instruction should be written into R 1 first , and then the content of R 1 should be read out in the I 2 instruction . Since I 2 instruction enters the pipeline, it becomes I 2 instructions in the instruction I I . 1 write R & lt . 1 studied before an R & lt . 1 content, data hazard occurs. ↵
18. What are the two implementation methods of the CPU controller? What are the advantages and disadvantages of each?
Answer: One isHard-wired line controller,two isMicroprogram controller。
The advantage of the hard-wired line controller is that it is fast and suitable for implementing a simple or regular command system. The disadvantage is that it is a huge logic network with multiple inputs and multiple outputs, with a complex structure, difficult to implement and difficult to maintain.
The microprogram controller adopts the principle of stored program, so every instruction must be fetched from the control storage once. It is characterized by regularity, easy maintenance, and flexibility, but its speed is slow.
19. A certain disk has 2 platters (double-sided), 10,000 cylinders, each track has 400 sectors on average, and each sector has 512 bytes. Calculate the disk capacity.
Answer: Disk capacity=512 400 10000 2 2=8192000000B=8.192GB
20. In a C language program, why the final f value of the following program segment is 0 instead of 2.5?
float f=2.5+1e10;↵
f= f-1e10;
Answer: First of all, the float type is expressed in the IEEE 754 single-precision floating-point number format. Therefore, there are up to 24 binary significant digits.
Because 1e10=10 10 , it is roughly equivalent to 2 33 in the number mile level , and the number mile level of 2.5 is 21. Therefore, when calculating 2.5+1e10 for the order, the difference between the two number order codes is 32, that is , The mantissa of 2.5 should be shifted to the right by 32 bits, so that all the 24 significant digits are lost, and the mantissa becomes all 0. When added to the mantissa of 1e10, the result is the mantissa of 1e10, so the result of f=2S+1e10 is still Is 1e10, so the result is 0 when f=f-1e10 is executed again.
21. How are I/O ports addressed? And explain separately.
Answer: The two addressing methods areIndependent addressingwithUnified addressing. alone
The independent addressing is the number of the IO port and the main memory unit respectively, and does not occupy the address space of the main memory unit. The IO port and the main memory unit may have the same number, so special IO instructions are required;
Unified addressing refers to the different positions of the IO port and the main memory unit in the same address space. It can be distinguished whether the I0 port or the main memory unit is accessed according to the address range, so no special IO instructions are required.
23. The following is a sequence of MIPS instructions:
1 add $t1,$s1,$s0
2 sub $T2,$s0,$s3
3 add $t1,$t1,$t2
Assuming that the above instruction sequence is executed in a 5-stage pipeline processor that uses "fetch instruction, decode/fetch, execute, fetch, and write back", please answer the following questions: ↵
(1) In the above instruction sequence, which instructions have data correlation?↵
(2) If the "forwarding" technology is not used, where and how many R. instructions need to be added to enable the execution of this sequence of instructions to avoid data hazards?↵
(3) If the "forwarding" technology is adopted, can the data hazard be completely resolved?↵
Answer: (1) Data correlation occurs between the first and third instructions, and the second and third instructions.
(2) If "forwarding" is not performed, 3 or 2 nor instructions must be inserted between the second and third instructions: if the register writer and register read are only arranged one clock cycle before, In the second half of the cycle, work independently only needs to add 2 plus, otherwise it is 3.
(3) Using "forwarding" technology, the above program segment can completely avoid data hazards.