Learning FPGA development is the only way for ordinary hardware engineers to develop into senior hardware engineers. With the increasing integration of chips, traditional hardware engineers can do less and less work. Is there no future for hardware engineers?
With the increasing integration of FPGAs, and the increasing demand for large amounts of data/large amounts of computing in the application market, the integration route of ARM+FPGA will become the mainstream trend of future chip development. Mastering the development skills of this heterogeneous platform is also one of the ways for hardware engineers to improve their own capabilities.
Let's start with a simple Verilog program. Today's main task is to be familiar with the operation process of vivado.
Project creation
The installation of the vivado software will not be introduced in this article. The following assumes that you have already installed vivado on your computer. I am using the 2016.1 version. The operations of different versions are similar.
Double-click the desktop shortcut, and it is the
first time you use this look , so click on the new project in the upper left corner and name it project_led. Save the path. I like to create a folder called MyProject under the EDA installation path. .
In the next interface, we choose RTL project, because it is the first design from the low-level design method of verilog language.
Choose the chip model according to the board you have. Of course, it’s okay not to choose it here. I believe that those comrades who can start using vivado will have some experience in using other FPGA development programs. The chip model can also be set in the following steps.
After everything is ready, you can see the interface shown in the figure below. The orange window in the upper middle contains the file information of the entire project, including design documents, constraint documents and simulation documents.
Add design files
We are on the leftmost side of the software and find Project Manag at the top. The first Projec Setting can set or modify the chip model and basic project settings. Click the second Add Sources
pop-up window to select the second one
in the new pop-up In the window, select Creat File,
select the file type Verilog, enter the file name led_test
, you can see the file information in the new window, click Finish
, and then enter the name of the module, which is also led_test
Project Manage. You can see one more file
after double-clicking and opening A blank verilog file, click the upper right corner of the window to switch the size of the window.
Enter the code below
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/07/08 16:59:19
// Design Name:
// Module Name: led_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module led_test(
input CLK_i,
input RSTn_i,
output reg [3:0]LED_o
);
reg [31:0]CNT; //时钟计数counter
always @(posedge CLK_i)
if(!RSTn_i)
begin
LED_o <= 4'b1;
CNT <= 32'h0;
end
else
begin
if(CNT == 32'd50_000_000)
begin
CNT <= 32'h0;
if(LED_o == 4'b1000)
LED_o <= 4'b1;
else LED_o <= LED_o << 1;
end
else
begin
CNT <= CNT + 1'b1;
LED_o <= LED_o;
end
end
endmodule
Compile and configure
Click the synthesis icon on the top or the left to start synthesis. After synthesis, a small interface will pop up to remind you what to do next. You can click cancel and implement it after assigning pins.
Find the Project Manage on the leftmost side of the window again, and add the file, but this time the constraint file is added, select the first one.
See the familiar interface again, choose Creat File. The
input file name is still led_test, but this time the file type is XDC, constraint file. The so-called constraints refer to information such as the pin, signal characteristics, and pin level of the specified signal.
In the next step, I have seen it. Continue to Finish
Project Manage and see another file.
Next, we can double-click the xdc file and enter the constraints in the text format, or set by options. We use the second one.
First found in the left-most column of the window synthesis, the bottom has a Schema'tic, click on it
you can see the following window, click on the top of the I / O Ports
at the bottom you can see the familiar interface, pin it manually specify the
designated Afterwards, remember to click Save in the upper left corner of the window. The
effect is like this. Here, I forgot to specify the level type of the pin. An error is prompted during compilation. You cannot choose default! You need to go back and manually modify it yourself.
Or find the schematic from the leftmost synthesis column and at the bottom.
Now synthesize/generate bit files
Download and run
Find the leftmost, bottom, bottom of the window!
The circuit board is plugged into the JTAG programmer, and the target board is powered on.
If the link is correct, you will see the following look. If the device is not found, please check the hardware connection.
Find the bottom of the left side of the window again and start programming; you can also right-click on the device name to start programming,
select the file path, and
witness the joy of success!
So far, a simple verilog has been successfully programmed, downloaded and run successfully in the vivado environment!
Familiar with vivado
Go back and familiarize yourself with vivado. Under RTL analysis, click on schematic to see
the effect of the register-level schematic synthesis. Pay attention to the location of the first step. If you choose different here, the comprehensive schematic will be different. Compare the following two pictures.
Have fun for a while!