Small experiment

VHDL Comprehensive Exercises
One, the purpose of the experiment

1. Master the basic programming methods of VHDL;
2. Master the VHDL design of some common circuits;
3. Review Quartus II design compilation and simulation verification.
   2. Experimental requirements
4. Complete the design of decimal counter with VHDL language.
5. The design of a 10-frequency divider with a 50% duty cycle is completed in VHDL language.
6. Use VHDL language to complete the design of the display decoder driving the common cathode digital tube.
7. Compile and simulate on the Quartus II software platform.
   3. Main instrument and equipment
   Computer, Quartus Ⅱ software platform
   4. Experiment content 1.
   Decimal counter program
   (1) Input text:
   library ieee;
   use ieee.std_logic_1164.all;
   use ieee.std_logic_unsigned.all;

entity cnt10 is
port(
clk:in std_logic;
en :out std_logic;
y:out integer range 0 to 10);
end cnt10;
architecture a of cnt10 is
signal q_temp: integer range 0 to 10;
begin
process(clk)
begin
if(clk’event and clk=‘1’)then
if
q_temp = 9 then
en <= ‘1’;
q_temp <= 0;

	else
		 q_temp <= q_temp+1;
		 en <= '0';
      
	end if;
end if;

y<=q_temp;
end process;
end a;;
（2）仿真

2.10 Frequency divider program
(1) Input text:
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;

Entity fdiv is
generic(N: integer:=10); --rate=N，baiN是偶数
port(
clkin: IN std_logic;
clkout: OUT std_logic
);
End fdiv;
Architecture a of fdiv is
signal cnt: integer range 0 to n-1;
Begin
process(clkin) --计数
begin
if(clkin’event and clkin=‘1’) then
if(cnt<n-1) then
cnt <= cnt+1;
else
cnt <= 0;
end if;
end if;
end process;

process(cnt) --Control the high and low levels of the output clock pulse according to the counter value du.
begin
if(cnt<n/2) then
clkout <= '1';
else
clkout <= '0';
end if;
end process;

End a;
(2) Simulation

3.显示译码器程序
（1）输入文本：
Library ieee;
Use ieee.std_logic_1164.all;
Entity QELED7 is
PORT(DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
a,b,c,d,e,f,g:out std_logic);
end QELED7;
Architecture LED of QELED7 is
signal y: STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
process(DATA)
begin
case DATA is
when “0000”=>y<=“1111110” ;
when “0001”=>y<=“0110000” ;
when “0010”=>y<=“1101101” ;
when “0011”=>y<=“1111001” ;
when “0100”=>y<=“0110011” ;
when “0101”=>y<=“1011011” ;
when “0110”=>y<=“1011111” ;
when “0111”=>y<=“1110000” ;
when “1000”=>y<=“1111111” ;
when “1001”=>y<=“1111011” ;
when others=>null;
end case;
a<=y(6);b<=y(5);c<=y(4);
d<=y(3);e<=y(2);f<=y(1);g<=y(0);
end process;
end;
（2）仿真

5. Experimental results and analysis
(1) Decimal counter
When the rising edge of the clock comes, the count is increased by one. When the count is 9 (0111), the counter is cleared when the next rising edge of the clock comes, and a clock cycle carry signal is generated.

(2) A 10-frequency divider with a duty cycle of 50%
. As shown in the figure, the experimental results are correct. Set a 5-ary counter. When it is full, the output signal is inverted, that is, the output cycle is performed once every 10 cycles. Signal, to achieve a 10-divider with a 50% duty cycle.

3) Display decoder driving common cathode digital tube

The common cathode is working at a high level, so when it is 0, it is all high level except for g. It can display 0 and
other numbers can be deduced by analogy. The picture shows that my experiment results are correct