USIO UART receive flag and interrupt
The UART receiver has a flag to indicate the state of the receiver.
Reception completion (RXC0) flag bit indicates whether there are unread data in the receive buffer. When the receiving buffer has the data value bits are not read, when the receiving buffer clearing position zero. If the receiver is disabled (RXE0 = 0), and the receiving buffer is emptied RXC0 cleared.
When receiving the completion USI0CR2 register interrupt enable bit (RXCIE0) the total value of the bit while the interrupt is opened, RXC0 flag value of bit UART reception completion interrupt generates an interrupt.
The UART receiver has three error flag, framing error, respectively (FR0), data beyond (DOR0), and parity error (PE0). The error flag may be read by USI0ST1 register. Storing the received data in the reception stage register 2, these flags are also stored in the same location of the receive buffer. Therefore, before accepting read data from the register USI0DR, USI0ST1 first read register contains an error flag.
Frame format error (FE0) flag represents the first stop bit. When the monitoring stop bit to the right to '1', PF0 is '0' when the stop bit error, 0 is detected, the FE is "1". This bit may be a loss of synchronization between the data detected from frame to frame .
Data beyond (DOR0) flag indicates that the data because the receive buffer is full caused by the loss. When the receiving buffer is full, while the other has been stored in the reception buffer and the new data is present in the receive shift register, DOR0 generated. When DOR0 bit flag value, all incoming data is lost. Avoid data loss or the bit is cleared, the read receive buffer.
Parity error (PE0) flag bit indicates that data reception has been received temporary area has a parity error. If parity detection function is not enabled (USI0PM1 = 0), PE0 bits are usually read '0'.
USI0 UART Parity
If the parity bit is enabled (USI0PM1 = 1), calculates the parity-check incoming data and the received parity compares the serial data frame.
USI0 UART receive disabled
In contrast to the transmission, it can be disabled by clearing RXE0 receiver enables the receiver performs immediately. When the receiver is disabled, the receiver buffer is empty, all the remaining data in the buffer is reset, while RXD0 pin as normal I / O port (GPIO).
