Outline
MC96F6432S has eight separate runs a basic interval timer can not be stopped, as shown, it also provides a baseline scan watchdog counter, a basic interval timer interrupt (BITIFR).
MC96F6432S interval timer characteristics substantially as follows:
- During power-On, BIT gives a stable clock time
- Launched Stop mode, BIT provides a stable clock pulse time
- Use as a timer, the timer interrupt is generated
Block diagram
FIG Register
Register Description BIT
A basic interval register and BITCR bitCnt composition BCLR if the bit is set to '1', BITCNT becomes '0' and starts counting. After one machine cycle, BCRLR bit is automatically cleared.
BIT register
