UVM verification platform often implemented driver, monitor, sequencer and other base classes for later use, and encapsulating agent to its base class which, because the monitor monitored xaction passed to rm, scoreboard and other components.
Unified connection uvm_tlm_analysis_fifo name of the port, and avoid path too, increase analysis_port agent in them, and this monitor in analysis_port pointing agent in analysis_port.
When use is to be noted that when connect_phase, needs to be connected via the connect them together, otherwise the data can not be transmitted to other components.
Figure I
Figure II 
can be seen in the above two pictures at the time of connection, connected to the unified mon_port; Without a map of the line25 connect, scoreboard can not receive data.
