1.问题描述：
随着我国移动电视和多媒体广播技术（CMMB）的不断进步，其标准所采用的信道纠错编码技术——低密度奇偶校验码（LDPC）技术也得到了越来越多的研究者的关注，由于LDPC码是一种性能较高的纠错编码，使其在基于可靠性信号传输方面具有非常广阔的应用前景。从LDPC码的基础理论出发，在研究前人成果的基础上，针对CMMB标准，采取理论阐述、算法仿真等方式进行了LDPC码的构造方式分析、编码技术分析和译码算法仿真比较，并最终以综合性能较好的最小和译码算法作为基础，对CMMB标准环境下的LDPC码校验矩阵的特点进行分析，据此特点对译码器进行了设计，设计过程避免了单一使用并行结构或串行结构的方式，而是采用将二者结合的方法，最后在设计的基础上完成了译码器的具体实现。研究对LDPC译码器所采取的独特的设计结构以及存储器的控制策略，在保证速度的前提下增强了性能，从而实现了以小资源换取高性能的目标。
2.部分程序：
`timescale 1 ns / 1 ps
module ldpc_dec(
i_sys_clock, //系统时钟
i_sys_rst, //系统复位
i_ldpc_data, //系统编码数据
i_ldpc_enable,//系统帧使能信号
i_ldpc_rate, //系统码率
o_ldpc_data, //系统译码后的数据
o_ldpc_enable,//系统译码后的使能
o_IsWorking, //系统工作使能
dout00,dout01,dout02,dout03,dout04,dout05,
dout06,dout07,dout08,dout09,dout10,dout11,
dout12,dout13,dout14,dout15,dout16,dout17,
dout18,dout19,dout20,dout21,dout22,dout23,
dout24,dout25,dout26,dout27,dout28,dout29,
dout30,dout31,dout32,dout33,dout34,dout35,//每个RAM中的输出
//读写地址输出测试
ADDRESS_WRITE_ENABLE00,ADDRESS_WRITE_ENABLE01,ADDRESS_WRITE_ENABLE02,ADDRESS_WRITE_ENABLE03,ADDRESS_WRITE_ENABLE04,ADDRESS_WRITE_ENABLE05,
ADDRESS_WRITE_ENABLE06,ADDRESS_WRITE_ENABLE07,ADDRESS_WRITE_ENABLE08,ADDRESS_WRITE_ENABLE09,ADDRESS_WRITE_ENABLE10,ADDRESS_WRITE_ENABLE11,
ADDRESS_WRITE_ENABLE12,ADDRESS_WRITE_ENABLE13,ADDRESS_WRITE_ENABLE14,ADDRESS_WRITE_ENABLE15,ADDRESS_WRITE_ENABLE16,ADDRESS_WRITE_ENABLE17,
ADDRESS_WRITE_ENABLE18,ADDRESS_WRITE_ENABLE19,ADDRESS_WRITE_ENABLE20,ADDRESS_WRITE_ENABLE21,ADDRESS_WRITE_ENABLE22,ADDRESS_WRITE_ENABLE23,
ADDRESS_WRITE_ENABLE24,ADDRESS_WRITE_ENABLE25,ADDRESS_WRITE_ENABLE26,ADDRESS_WRITE_ENABLE27,ADDRESS_WRITE_ENABLE28,ADDRESS_WRITE_ENABLE29,
ADDRESS_WRITE_ENABLE30,ADDRESS_WRITE_ENABLE31,ADDRESS_WRITE_ENABLE32,ADDRESS_WRITE_ENABLE33,ADDRESS_WRITE_ENABLE34,ADDRESS_WRITE_ENABLE35,
ADDRESS_READ_ENABLE00,ADDRESS_READ_ENABLE01,ADDRESS_READ_ENABLE02,ADDRESS_READ_ENABLE03,ADDRESS_READ_ENABLE04,ADDRESS_READ_ENABLE05,
ADDRESS_READ_ENABLE06,ADDRESS_READ_ENABLE07,ADDRESS_READ_ENABLE08,ADDRESS_READ_ENABLE09,ADDRESS_READ_ENABLE10,ADDRESS_READ_ENABLE11,
ADDRESS_READ_ENABLE12,ADDRESS_READ_ENABLE13,ADDRESS_READ_ENABLE14,ADDRESS_READ_ENABLE15,ADDRESS_READ_ENABLE16,ADDRESS_READ_ENABLE17,
ADDRESS_READ_ENABLE18,ADDRESS_READ_ENABLE19,ADDRESS_READ_ENABLE20,ADDRESS_READ_ENABLE21,ADDRESS_READ_ENABLE22,ADDRESS_READ_ENABLE23,
ADDRESS_READ_ENABLE24,ADDRESS_READ_ENABLE25,ADDRESS_READ_ENABLE26,ADDRESS_READ_ENABLE27,ADDRESS_READ_ENABLE28,ADDRESS_READ_ENABLE29,
ADDRESS_READ_ENABLE30,ADDRESS_READ_ENABLE31,ADDRESS_READ_ENABLE32,ADDRESS_READ_ENABLE33,ADDRESS_READ_ENABLE34,ADDRESS_READ_ENABLE35
);
input i_sys_clock;
input i_sys_rst;
input i_ldpc_rate;
input[5:0]i_ldpc_data;
input i_ldpc_enable;
output o_ldpc_data;
output o_ldpc_enable;
output o_IsWorking;
output[7:0]dout00,dout01,dout02,dout03,dout04,dout05,
dout06,dout07,dout08,dout09,dout10,dout11,
dout12,dout13,dout14,dout15,dout16,dout17,
dout18,dout19,dout20,dout21,dout22,dout23,
dout24,dout25,dout26,dout27,dout28,dout29,
dout30,dout31,dout32,dout33,dout34,dout35;
output[7:0]ADDRESS_WRITE_ENABLE00,ADDRESS_WRITE_ENABLE01,ADDRESS_WRITE_ENABLE02,ADDRESS_WRITE_ENABLE03,ADDRESS_WRITE_ENABLE04,ADDRESS_WRITE_ENABLE05,
ADDRESS_WRITE_ENABLE06,ADDRESS_WRITE_ENABLE07,ADDRESS_WRITE_ENABLE08,ADDRESS_WRITE_ENABLE09,ADDRESS_WRITE_ENABLE10,ADDRESS_WRITE_ENABLE11,
ADDRESS_WRITE_ENABLE12,ADDRESS_WRITE_ENABLE13,ADDRESS_WRITE_ENABLE14,ADDRESS_WRITE_ENABLE15,ADDRESS_WRITE_ENABLE16,ADDRESS_WRITE_ENABLE17,
ADDRESS_WRITE_ENABLE18,ADDRESS_WRITE_ENABLE19,ADDRESS_WRITE_ENABLE20,ADDRESS_WRITE_ENABLE21,ADDRESS_WRITE_ENABLE22,ADDRESS_WRITE_ENABLE23,
ADDRESS_WRITE_ENABLE24,ADDRESS_WRITE_ENABLE25,ADDRESS_WRITE_ENABLE26,ADDRESS_WRITE_ENABLE27,ADDRESS_WRITE_ENABLE28,ADDRESS_WRITE_ENABLE29,
ADDRESS_WRITE_ENABLE30,ADDRESS_WRITE_ENABLE31,ADDRESS_WRITE_ENABLE32,ADDRESS_WRITE_ENABLE33,ADDRESS_WRITE_ENABLE34,ADDRESS_WRITE_ENABLE35;
output[7:0]ADDRESS_READ_ENABLE00,ADDRESS_READ_ENABLE01,ADDRESS_READ_ENABLE02,ADDRESS_READ_ENABLE03,ADDRESS_READ_ENABLE04,ADDRESS_READ_ENABLE05,
ADDRESS_READ_ENABLE06,ADDRESS_READ_ENABLE07,ADDRESS_READ_ENABLE08,ADDRESS_READ_ENABLE09,ADDRESS_READ_ENABLE10,ADDRESS_READ_ENABLE11,
ADDRESS_READ_ENABLE12,ADDRESS_READ_ENABLE13,ADDRESS_READ_ENABLE14,ADDRESS_READ_ENABLE15,ADDRESS_READ_ENABLE16,ADDRESS_READ_ENABLE17,
ADDRESS_READ_ENABLE18,ADDRESS_READ_ENABLE19,ADDRESS_READ_ENABLE20,ADDRESS_READ_ENABLE21,ADDRESS_READ_ENABLE22,ADDRESS_READ_ENABLE23,
ADDRESS_READ_ENABLE24,ADDRESS_READ_ENABLE25,ADDRESS_READ_ENABLE26,ADDRESS_READ_ENABLE27,ADDRESS_READ_ENABLE28,ADDRESS_READ_ENABLE29,
ADDRESS_READ_ENABLE30,ADDRESS_READ_ENABLE31,ADDRESS_READ_ENABLE32,ADDRESS_READ_ENABLE33,ADDRESS_READ_ENABLE34,ADDRESS_READ_ENABLE35;
`include "tops_DEFINE.txt"
always @(posedge i_sys_clock or negedge i_sys_rst)
begin
if(!i_sys_rst)
begin
enable_cnter <= 6'd0;
end
else if(i_ldpc_enable)
begin
if(enable_cnter == 6'd35)
enable_cnter <= 6'd0;
else
enable_cnter <= enable_cnter + 1'b1;
end
end
always @(posedge i_sys_clock or negedge i_sys_rst)
begin
if(!i_sys_rst)
begin
enable_delay <= 36'd0;
end
else if(i_ldpc_enable)
begin
enable_delay <= {enable_delay[34:0],i_ldpc_enable6 };
end
else begin
enable_delay <= 36'd0;
end
end
always @(posedge i_sys_clock or negedge i_sys_rst)
begin
if(!i_sys_rst)
begin
data_delay <= 8'd0;
end
else begin
data_delay <= {
{2{i_ldpc_data[5]}},i_ldpc_data};
end
end
always @(posedge i_sys_clock or negedge i_sys_rst)
begin
if(!i_sys_rst)
begin
out_sel_delay <= 36'd0;
end
else begin
out_sel_delay <= out_sel;
end
end
always @(posedge i_sys_clock or negedge i_sys_rst)
begin
if(!i_sys_rst)
begin
out_en_delay <= 1'b0;
o_ldpc_enable <= 1'b0;
end
else begin
out_en_delay <= out_en;
o_ldpc_enable <= out_en_delay;
end
end
`include "tops_RAM256x36.txt"
ldpc_controller ldpc_controller_u(
.i_sys_clk (i_sys_clock ),
.i_sys_rst (i_sys_rst ),
.i_frame_enable (i_ldpc_enable ),
.i_encode_rate (i_ldpc_rate ),
.i_max_iteration (5'd100 ),
.i_din (ctv_out ),
.i_sigma (sigmaer ),
.o_state (i_state ),
.o_move (MOVE ),
.o_isWorking (o_IsWorking ),
.o_interation (iter_0 ),
.o_Lq_write_enable(wr_lq ),
.o_Lr_write_enable(wr_lr ),
.o_Lq_read_enable (rd_lq ),
.o_Lr_read_enable (rd_lr )
);
Addresser Addresser_u(
.i_sys_clk (i_sys_clock ),
.i_sys_rst (i_sys_rst ),
.i_state (i_state ),
.i_move (MOVE ),
.i_dec_rate (i_ldpc_rate ),
.i_enable (enable_delay ),
.i_LQ_write_enable(wr_lq ),
.i_LR_write_enable(wr_lr ),
.i_LQ_read_enable (rd_lq ),
.i_LR_read_enable (rd_lr ),
.o_out_sel (out_sel ),
.o_out_en (out_en ),
.Address_read_enable00(ADDRESS_READ_ENABLE00),.Address_read_enable01(ADDRESS_READ_ENABLE01),.Address_read_enable02(ADDRESS_READ_ENABLE02),.Address_read_enable03(ADDRESS_READ_ENABLE03),
.Address_read_enable04(ADDRESS_READ_ENABLE04),.Address_read_enable05(ADDRESS_READ_ENABLE05),.Address_read_enable06(ADDRESS_READ_ENABLE06),.Address_read_enable07(ADDRESS_READ_ENABLE07),
.Address_read_enable08(ADDRESS_READ_ENABLE08),.Address_read_enable09(ADDRESS_READ_ENABLE09),.Address_read_enable10(ADDRESS_READ_ENABLE10),.Address_read_enable11(ADDRESS_READ_ENABLE11),
.Address_read_enable12(ADDRESS_READ_ENABLE12),.Address_read_enable13(ADDRESS_READ_ENABLE13),.Address_read_enable14(ADDRESS_READ_ENABLE14),.Address_read_enable15(ADDRESS_READ_ENABLE15),
.Address_read_enable16(ADDRESS_READ_ENABLE16),.Address_read_enable17(ADDRESS_READ_ENABLE17),.Address_read_enable18(ADDRESS_READ_ENABLE18),.Address_read_enable19(ADDRESS_READ_ENABLE19),
.Address_read_enable20(ADDRESS_READ_ENABLE20),.Address_read_enable21(ADDRESS_READ_ENABLE21),.Address_read_enable22(ADDRESS_READ_ENABLE22),.Address_read_enable23(ADDRESS_READ_ENABLE23),
.Address_read_enable24(ADDRESS_READ_ENABLE24),.Address_read_enable25(ADDRESS_READ_ENABLE25),.Address_read_enable26(ADDRESS_READ_ENABLE26),.Address_read_enable27(ADDRESS_READ_ENABLE27),
.Address_read_enable28(ADDRESS_READ_ENABLE28),.Address_read_enable29(ADDRESS_READ_ENABLE29),.Address_read_enable30(ADDRESS_READ_ENABLE30),.Address_read_enable31(ADDRESS_READ_ENABLE31),
.Address_read_enable32(ADDRESS_READ_ENABLE32),.Address_read_enable33(ADDRESS_READ_ENABLE33),.Address_read_enable34(ADDRESS_READ_ENABLE34),.Address_read_enable35(ADDRESS_READ_ENABLE35),
.Address_write_enable00(ADDRESS_WRITE_ENABLE00),.Address_write_enable01(ADDRESS_WRITE_ENABLE01),.Address_write_enable02(ADDRESS_WRITE_ENABLE02),.Address_write_enable03(ADDRESS_WRITE_ENABLE03),
.Address_write_enable04(ADDRESS_WRITE_ENABLE04),.Address_write_enable05(ADDRESS_WRITE_ENABLE05),.Address_write_enable06(ADDRESS_WRITE_ENABLE06),.Address_write_enable07(ADDRESS_WRITE_ENABLE07),
.Address_write_enable08(ADDRESS_WRITE_ENABLE08),.Address_write_enable09(ADDRESS_WRITE_ENABLE09),.Address_write_enable10(ADDRESS_WRITE_ENABLE10),.Address_write_enable11(ADDRESS_WRITE_ENABLE11),
.Address_write_enable12(ADDRESS_WRITE_ENABLE12),.Address_write_enable13(ADDRESS_WRITE_ENABLE13),.Address_write_enable14(ADDRESS_WRITE_ENABLE14),.Address_write_enable15(ADDRESS_WRITE_ENABLE15),
.Address_write_enable16(ADDRESS_WRITE_ENABLE16),.Address_write_enable17(ADDRESS_WRITE_ENABLE17),.Address_write_enable18(ADDRESS_WRITE_ENABLE18),.Address_write_enable19(ADDRESS_WRITE_ENABLE19),
.Address_write_enable20(ADDRESS_WRITE_ENABLE20),.Address_write_enable21(ADDRESS_WRITE_ENABLE21),.Address_write_enable22(ADDRESS_WRITE_ENABLE22),.Address_write_enable23(ADDRESS_WRITE_ENABLE23),
.Address_write_enable24(ADDRESS_WRITE_ENABLE24),.Address_write_enable25(ADDRESS_WRITE_ENABLE25),.Address_write_enable26(ADDRESS_WRITE_ENABLE26),.Address_write_enable27(ADDRESS_WRITE_ENABLE27),
.Address_write_enable28(ADDRESS_WRITE_ENABLE28),.Address_write_enable29(ADDRESS_WRITE_ENABLE29),.Address_write_enable30(ADDRESS_WRITE_ENABLE30),.Address_write_enable31(ADDRESS_WRITE_ENABLE31),
.Address_write_enable32(ADDRESS_WRITE_ENABLE32),.Address_write_enable33(ADDRESS_WRITE_ENABLE33),.Address_write_enable34(ADDRESS_WRITE_ENABLE34),.Address_write_enable35(ADDRESS_WRITE_ENABLE35),
.write_enable00(WRITE_ENABLE00),.write_enable01(WRITE_ENABLE01),.write_enable02(WRITE_ENABLE02),.write_enable03(WRITE_ENABLE03),.write_enable04(WRITE_ENABLE04),.write_enable05(WRITE_ENABLE05),
.write_enable06(WRITE_ENABLE06),.write_enable07(WRITE_ENABLE07),.write_enable08(WRITE_ENABLE08),.write_enable09(WRITE_ENABLE09),.write_enable10(WRITE_ENABLE10),.write_enable11(WRITE_ENABLE11),
.write_enable12(WRITE_ENABLE12),.write_enable13(WRITE_ENABLE13),.write_enable14(WRITE_ENABLE14),.write_enable15(WRITE_ENABLE15),.write_enable16(WRITE_ENABLE16),.write_enable17(WRITE_ENABLE17),
.write_enable18(WRITE_ENABLE18),.write_enable19(WRITE_ENABLE19),.write_enable20(WRITE_ENABLE20),.write_enable21(WRITE_ENABLE21),.write_enable22(WRITE_ENABLE22),.write_enable23(WRITE_ENABLE23),
.write_enable24(WRITE_ENABLE24),.write_enable25(WRITE_ENABLE25),.write_enable26(WRITE_ENABLE26),.write_enable27(WRITE_ENABLE27),.write_enable28(WRITE_ENABLE28),.write_enable29(WRITE_ENABLE29),
.write_enable30(WRITE_ENABLE30),.write_enable31(WRITE_ENABLE31),.write_enable32(WRITE_ENABLE32),.write_enable33(WRITE_ENABLE33),.write_enable34(WRITE_ENABLE34),.write_enable35(WRITE_ENABLE35),
.Address_read_enable (ADDRESS_READ_ENABLE ),
.Address_write_enable(ADDRESS_WRITE_ENABLE ),
.write_enable0 (WRITE_ENABLE0 )
);
Dec_ldpc_data Dec_ldpc_data_u(
.i_sys_clk (i_sys_clock ),
.i_sys_rst (i_sys_rst ),
.i_dec_state (i_state ),
.i_Move (MOVE[3:2] ),
.i_dec_rate (i_ldpc_rate ),
.i_interation(iter_0 ),
.i_enable (enable_delay ),
.i_din (data_delay ),
.o_ctv (ctv_out ),
.o_sigma (sigmaer ),
.dout00(dout00),.dout01(dout01),.dout02(dout02),.dout03(dout03),.dout04(dout04),.dout05(dout05),
.dout06(dout06),.dout07(dout07),.dout08(dout08),.dout09(dout09),.dout10(dout10),.dout11(dout11),
.dout12(dout12),.dout13(dout13),.dout14(dout14),.dout15(dout15),.dout16(dout16),.dout17(dout17),
.dout18(dout18),.dout19(dout19),.dout20(dout20),.dout21(dout21),.dout22(dout22),.dout23(dout23),
.dout24(dout24),.dout25(dout25),.dout26(dout26),.dout27(dout27),.dout28(dout28),.dout29(dout29),
.dout30(dout30),.dout31(dout31),.dout32(dout32),.dout33(dout33),.dout34(dout34),.dout35(dout35),
.din00 (din00 ),.din01 (din01 ),.din02 (din02 ),.din03 (din03 ),.din04 (din04 ),.din05 (din05 ),
.din06 (din06 ),.din07 (din07 ),.din08 (din08 ),.din09 (din09 ),.din10 (din10 ),.din11 (din11 ),
.din12 (din12 ),.din13 (din13 ),.din14 (din14 ),.din15 (din15 ),.din16 (din16 ),.din17 (din17 ),
.din18 (din18 ),.din19 (din19 ),.din20 (din20 ),.din21 (din21 ),.din22 (din22 ),.din23 (din23 ),
.din24 (din24 ),.din25 (din25 ),.din26 (din26 ),.din27 (din27 ),.din28 (din28 ),.din29 (din29 ),
.din30 (din30 ),.din31 (din31 ),.din32 (din32 ),.din33 (din33 ),.din34 (din34 ),.din35 (din35 ),
.Menory_din0 (Memory_din0 ),
.Menory_dout0 (Memory_dout0 ),
.Menory_din1 (Memory_din1 ),
.Menory_dout1 (Memory_dout1 ),
.Menory_din2 (Memory_din2 ),
.Menory_dout2 (Memory_dout2 )
);
ram_256x36u ram_256x36u0(
.i_clk_read(i_sys_clock),.i_clk_write(i_sys_clock),
.i_address_read(ADDRESS_READ_ENABLE),.i_address_write(ADDRESS_WRITE_ENABLE),
.i_enable_read(1'b1),.i_enable_write(1'b1),.i_different_write_enable(WRITE_ENABLE0),
.i_din(Memory_din0),
.o_dout(Memory_dout0)
);
ram_256x36u ram_256x36u1(
.i_clk_read(i_sys_clock),.i_clk_write(i_sys_clock),
.i_address_read(ADDRESS_READ_ENABLE),.i_address_write(ADDRESS_WRITE_ENABLE),
.i_enable_read(1'b1),.i_enable_write(1'b1),.i_different_write_enable(WRITE_ENABLE0),
.i_din(Memory_din1),
.o_dout(Memory_dout1)
);
ram_256x36u ram_256x36u2(
.i_clk_read(i_sys_clock),.i_clk_write(i_sys_clock),
.i_address_read(ADDRESS_READ_ENABLE),.i_address_write(ADDRESS_WRITE_ENABLE),
.i_enable_read(1'b1),.i_enable_write(1'b1),.i_different_write_enable(WRITE_ENABLE0),
.i_din(Memory_din2),
.o_dout(Memory_dout2)
);
..................................
default: dec_out = 1'b0;
endcase
always @(posedge i_sys_clock or negedge i_sys_rst)
begin
if(!i_sys_rst)
begin
o_ldpc_data <= 1'b0;
end
else if(out_en_delay)
begin
o_ldpc_data <= dec_out;
end
else o_ldpc_data <= 1'b0;
end
endmodule
3.仿真结论：
A-14-20