代码实现简单译码器与加法器

4-16译码器

module yimaqi(out,in);
   output [16-1:0] out;
   input [4-1:0] in;
   reg [16-1:0] out;
   always @(in)
   begin
     case(in)
     4'd0:  out=16'b1111111111111110;
     4'd1:  out=16'b1111111111111101;
     4'd2:  out=16'b1111111111111011;
     4'd3:  out=16'b1111111111110111;
     4'd4:  out=16'b1111111111101111;
     4'd5:  out=16'b1111111111011111;
     4'd6:  out=16'b1111111110111111;
     4'd7:  out=16'b1111111101111111;
     4'd8:  out=16'b1111111011111111;
     4'd9:  out=16'b1111110111111111;
     4'd10: out=16'b1111101111111111;
     4'd11: out=16'b1111011111111111;
     4'd12: out=16'b1110111111111111;
     4'd13: out=16'b1101111111111111;
     4'd14: out=16'b1011111111111111;
     4'd15: out=16'b0111111111111111;
     endcase
   end
 endmodule

输出波形最上边没有按16位二进制显示，没弄明白原因。
12加法器

module asum(out,count,clk);
    output [3:0]out;
    output count;
    input clk;
    reg [3:0] out;
    reg count;
always@(posedge clk)//clk上升沿触发
    begin
        count<=1'b0;
        if(out==11)
        begin
        count<=1'b1;
        out<=4'b0;
        end
        else 
            out<=out+1;
    end
endmodule

20加法器

module bsum(out,count,clk);
    output [4:0]out;
    output count;
    input clk;
    reg [4:0] out;
    reg count;
always@(posedge clk)//clk上升沿触发
    begin
        count<=1'b0;
        if(out==19)
        begin
        count<=1'b1;
        out<=4'b0;
        end
        else 
            out<=out+1;
    end
endmodule

来回计数

module UpDown_M9(out,count,clk);
    input clk;
    output [3:0]out;
    output count;
    reg [3:0] out;
    reg count=1;
always@(posedge clk)begin       //clk上升沿触发
    case(count)
    2'b1:           //count=1时递加，且加至9时count取反变0
        begin 
            out<=out+1;
            if (out==8)
            count=~count;
        end
    2'b0:           //count=0时递减，且减至0时count取反变1
        begin
            out<=out-1;
            if (out==1)
            count=~count;
        end
    endcase
end
endmodule