Recently, I am also working on RT1170-related projects. Due to the needs of the project, I have studied the Flash download algorithm, the erasing/programming of the NOR Flash space (the OTFAD Key Blob field must be updated when the OTFAD XIP updates the firmware), HyperRAM initialization and other functions. These are some problems that may be encountered during the development process, and these are closely related to the FlexSPI interface. After the FlexSPI is initialized, you can access the content in the external memory just like accessing the built-in memory such as ITCM and DTCM in the CPU. For FlexSPI1, it can map the external memory address to 0x30000000; while FlexSPI2 can map to 0x60000000.
1 FlexSPI block diagram
FlexSPI( Flexible Serial Peripheral Interface) supports two SPI channels and up to 4 external devices. Each channel supports bi-directional data transfer in Single/// Dualmode . Let's take a look at the functional block diagram of FlexSPI: (1) FA port and FB port FlexSPI can be connected to the external serial Flash through its two channels FA and FB. FA and FB each have two channels. For example, most HyperRAMs have eight data lines, which fill up one Port A/B. For QSPI NOR Flash, only four data lines are needed, so another device can be connected to Port A/B. (2) All external memories have their timings, and you can generate corresponding control timings to access external memories according to your configuration. Among them, there is a very important data structure, which is LUT( ), which is used to specify the timing of each operation of Flash.QuadOctal
SEQ_CTLSEQ_CTLLook Up Table
(3) AHB BUS 64bitandIPS BUS 32bit
32bit IPS BUS (that is, manually operate the FlexSPI register to send Flash read and write commands), 64bit AHB BUS (translate the AHB access address by FlexSPI and automatically send the corresponding Flash read and write commands)
AHB BUS 64bit: The user can access the external memory connected to the FlexSPI just like accessing the internal SRAM. At this time, the address is transmitted to theSEQ_CTLIPS BUS 32bit: The user can actively access the relevant registers of FlexSPI to complete some operations of the external memory according to the timing of each operation of the external memory initialized by himself (such as erasing, reading/writing memory, and reading/writing registers)
(4)ARB_CTL
Since both the AHB and IPS buses can request the data of the external memory, it ARB_CTLis used to control which bus can be executed first when the two buses access the external memory at the same time.
(5) Buffer
In order to speed up the reading speed, both buses have read and write buffers. AHB BusThere are send buffer AHB_TX_BUFand receive buffer AHB_RX_BUF, which will buffer the write data or read data of AHB burst transmission; and IPS Busthere are send buffer IP_TX_FIFOand receive buffer IP_RX_FIFO, both of which are 256 bytes in size and support DMA transfer.
2 FlexSPI Features
(1) SDR and DDR mode
In SDR( Single Data transfer Rate) mode, Flash receives data on the rising edge of SCLK and sends data on the falling edge. In DDR ( Dual Data transfer Rate) mode, Flash receives data and sends data on both the rising and falling edges of SCLK. SDR and DDR modes are determined by opcodes in the LUT table.
(2) In Individual and Parallel mode
,Individual mode Flash read/write data is completed on Port A or Port B. Nextparallel mode , the read and write operations of Flash are completed in parallel on Port A and Port B, and FlexSPI will automatically merge/split the data read and written by Flash. That is, data can be stored in two different Flash. Of course, on the hardware, there must be a corresponding connection.
- Only read and write commands can be automatically merged and split. For other commands (such as command/address/mode/data size), the same data will be transmitted to two Flash devices at the same time. For example, if a command is sent, both Flash devices will receive it. .
(3) Single, Dual, Quad, and Octal mode
- Single mode: Flash sends/receives data on the DATA0 pin
- Dual mode: Flash sends/receives data on DATA0~DATA1 pins
- Quad mode: Flash sends/receives data on DATA0~DATA3 pins
- Octal mode: Flash sends/receives data on DATA0~DATA7 pins
These modes are also determined in the LUT table.
(4) Operation mode
① Module Disable mode: Used for low power consumption mode, in this mode the AHB clock and serial clock domain will be turned off, but the IPS bus clock will not be turned off.
② Doze mode: Used for low power consumption mode. In this mode, FlexSPI will wait for all processing to complete before entering Doze mode. At this time, the AHB and serial clock domains will be turned off, but the IPS bus clock will not be turned off.
③ Stop mode: Used for low power consumption mode. In this mode, FlexSPI will wait for all processing to be completed, then return an ACK to the system, and then IP will turn off the AHB and serial clock domains. But AHB/IPS/serial clock can be turned on at system level.
④ Normal mode: All clocks will not be turned off.
3 summary
This section briefly introduces the functional block diagram and some features of FlexSPI. In fact, this is a general summary of the reference manual. For more details, please refer to the reference manual. For FlexSPI, the most important thing is the LUT form, so the next section will introduce the LUT form in detail.