Recently, because of the need, I learned the AXI bus protocol and DDR3-related knowledge, and spent a lot of time looking for various related information. I deeply understand that it is not easy to check the information. Here is a summary of what I have learned. Those who need it will provide some convenience, and those who have problems are welcome to discuss and learn together and make progress together.
1 AXI bus
First of all, let me talk about the knowledge about the AXI bus. When I first heard about AXI, I thought it was very complicated because I didn’t understand it. In fact, what I want to tell you is that when we learn about it, we will find that it is not It is not as complicated as imagined, and it is very similar to other buses, but it uses a different protocol.
1.1 Features of AXI bus
The AXI bus supports high-performance, high-frequency system design, and has the following characteristics: (1) It is suitable for high-bandwidth low-latency design, meets the interface of most devices, is suitable for memory controllers with high-speed demonstrations, and provides flexible interconnection structures Sexuality and independence, the country is compatible with the existing interfaces of AHB/APB. (2) It has separate address/control, data phases, (3) uses byte strobe and supports non-aligned data transfer. (4) Based on (BURST) burst transmission, only the first address needs to be transmitted. (5) The read and write data channels are separated, which can provide low-power DMA. (6) Support multiple addressing modes, support out-of-order transmission, easy to add register level for timing convergence, the design goal of AXI can run at high clock frequency, and can still achieve the highest data throughput under the condition of long delay time Rate. The AXI bus separates the read/write results, separates the data write and data read signals, and can perform write and read operations at the same time. In fact, the main point is that AXI is a high-performance bus, and its speed is very fast. Burst transmission means that after a first address is given, the remaining data will be transmitted sequentially, and the address corresponding to the transmission will increase according to the data bit width. For example, for 32bit data, the burst length is 16 (the burst length refers to is the number of data transmissions required for each burst transmission), then each time it transmits a data corresponding to 4BYTE, and the address increases by 4, then the address of a burst transmission will increase by 64.
1.2 Interconnection of AXI bus
As shown in the figure, the AXI protocol provides a single interface definition, which can be used between the following three interfaces: master/interconnect, slave/interconnect, and master/slave. In addition, it can use the following typical system topologies: (1) shared address and data bus; (2) shared address bus, multiple data bus; (3) multilayer multilayer, multiple address bus, multiple data bus.
In general, we have higher requirements for data bit width, but lower requirements for address bus, so we can adopt the structure of shared address bus and multi-data bus.
2 AXI signal description
2.1 Global Signals
Global signals include clock signals and reset signals.
2.1.1 Clock (ACLK)
Each AXI interface requires a global clock signal ACLK, and data transmission is based on this ACLK. On the master and slave interfaces, no combinational logic path can exist between the input signal and the output signal.
2.1.2 Reset (ARESETn)
The ARESETn signal is a global reset signal, active low. The description for it is this:
During reset: (1) The host interface must pull ARVALID, AWVALID, WVALID low; (2) The slave interface must pull RVALID, BVALID low; (3) Other signals can be any value. It is easy to understand that the earliest moment when the VALID signal is high is the rising edge of the first ACLK after the ARESETn signal is pulled high.
2.2 Other signals
AXI has five channels, and each channel has its own corresponding signal, but many of them are not usually used, so here are some more commonly used signals.
2.2.1 Write address channel signal
AWADDR is the write address, the first address of a burst write. AWLEN is the burst length, the number of burst write transfer data.
AWSIZE is the burst size, the number of bytes transferred per burst. AWBURST is a burst type, and there are three types: FIXED, INCR, and WRAP. AWVALID indicates that the address control signal of this channel is valid. AWREADY indicates that the slave device is ready to accept address and control information.
2.2.2 Write data channel signal
WDATA is the data sent from the write master to the slave. WSTRB is a valid byte line for writing data, which is used to indicate which 8bits of data are valid. It is similar to a strobe signal, which can set some bits of the written data to be invalid. WVALID indicates that the master is ready to send data to the slave. WREADY indicates that the slave can receive the data sent by the master.
2.2.3 Write response channel signal
BRESP is a write response signal, indicating the state of the write transaction, including OKAY, EXOKAY, SLVERR, and DECERR. BVALID indicates that the slave is ready to write the response signal. BREADY indicates that a write response signal can be received.
2.2.4 Read address channel signal
ARADDR is the read address, which represents the first address of a burst read. ARLEN is the burst length, the number of burst read transfer data. ARSIZE is the burst size, the number of bytes transferred per burst. ARBURST burst type, respectively FIXED, INCR, WRAP. ARVALID indicates that the address control information of this channel is valid. ARREADY indicates that the slave is ready to receive address and control information.
2.2.5 Read data channel signal
RDATA is the data read by the master from the slave. RRESP is a read response signal, indicating the status of the read transaction. RLAST is the last data in a burst read transfer. RVALID indicates that the slave is ready to read the data. RREADY indicates that the master can read data from the slave.
3 Five channels of AXI
As mentioned earlier, AXI separates the read and write channels, allowing simultaneous read/write operations. In fact, as shown in the figure below, AXI has five bidirectional flow control channels (through the VALID/READY handshake protocol, both parties can control the transmission rate). Borrowing other people's pictures here for illustration.
The AXI protocol is transmitted based on the VALID/READY handshake mechanism. When the VALID signal is high, it means that the sender's data is ready and can be sent; when the READY signal is high, it means that the receiver can receive data. Only when the VALID signal and the READY signal are high at the same time, the data can be transmitted.
Here is a handshake dependency that needs to be explained. The simple understanding is that there is no dependency between the VALID and READY signals, and whoever is ahead can be behind. Only when both signals are high at the same time, the handshake is successful.
After explaining the VALID/READY handshake mechanism, it is much easier to understand the five channels of AXI. AXI has five channels: write address channel, write data channel, write response channel, read address channel, and read data channel, which do not interfere with each other during transmission. Taking the write sequence as an example, when the host needs to send data to the slave, it first writes the address of the data to the slave after the handshake of the write address channel is successful, and then writes to the slave after the successful handshake of the write data channel. For the data to be sent, the WLAST signal represents the last data sent. Finally, after the write is successful, the slave returns a response signal to the master through the write response channel (at the same time, a successful handshake is required for transmission). The read timing is similar, but it should be noted that the read transmission also has a response signal, which is transmitted in the read data channel.
4 AXI burst transfer mechanism
The AXI bus is based on BURST transmission. The concept of the so-called burst transmission has been mentioned above, that is, given a burst length LEN, one transmission can transmit LEN data, and the address will be added according to the data bit width.
4.1 Transmission process
(1) Start address (AxADDR) -> burst transfer length (AxLEN) -> data width (AxSIZE) -> burst type (AxBURST).
(2) After receiving the start address, the slave receives and writes data or reads the data to the master at one time.
4.2 Burst transfer type
(1) FIXED: The starting address used by all data in the burst transfer.
(2) INCR: The address of the subsequent data is incremented on the basis of the initial address, and the increment is the same as the transmission width. (The most commonly used transmission type, assuming that the transmission data bit width is 32 bits, that is, the burst size is 4 bytes, the address is incremented by 4 each time; the data bit width can be 8, 16, 32, 64, 128, 256, 512, 1024 bits) .
(3) WRAP: First, the address of the wrapping boundary will be calculated based on the starting address, and after reaching this address, it will return to the starting address. In other cases, it is the same as the second type. The geological boundary can be calculated by the following formula:
Wrap_Boundary=(INT(Start_Address / (Number_Bytes x Burst_Length))) x (Number_Bytes x Burst_Length)
4.3 Burst Transfer Limitation
(1) In WRAP mode, the burst transmission length can only be 2, 4, 8, 16, while in INCR mode, the AXI4 interface can reach a burst length of 1~256.
(2) In a burst transfer, the address cannot cross the 4KB address boundary (4KB=4096BYTE).
(3) For a burst transmission, all data transmission must be completed and cannot be received in advance (some unwanted signals can be set to invalid through the WSTRB signal).
The above is an introduction to some common knowledge of AXI. For more content, you can refer to the following two blogs. I think they are very well written. There are many things that can only be understood after reading their articles. https://blog.csdn.net/ivy_reny/article/details/56274238
https://blog.csdn.net/meng1506789/article/details/111565579
In addition, you can find the explanation of AXI in the punctual atom ZYNQ series, which is more detailed.