Hello everyone, I am Wuji.
In the last chapter, we explained the definition of the spi interface. Today, we will explain the timing diagram of the spi protocol and the usage of the four modes of spi in more depth.
When I first came into contact with MCU development, I was most afraid of looking at the timing diagram, which is strange knowledge to me.
Especially for SPI and IIC, before writing programs, they directly copied other people's programs, and the functions were realized, and they did not study the timing of data transmission.
At that time, I was inexperienced, and the information I searched on the Internet was too academic, and I couldn't understand it.
After doing a lot of projects, I found that the most commonly used communication buses are nothing more than SPI, IIC, USART, CAN, and single-port communication.
The understanding has gradually deepened, and now it is clearer to analyze the timing diagram.
Therefore, I often instill a concept with the students of Wuji MCU programming, learn to use it first, and then it will be easier to use it more and gain more experience .
Don't die when you are inexperienced, otherwise you will pay a lot of unnecessary time costs.
Next, we enter the topic.
1. Detailed explanation of the four modes of spi
Before talking about the timing diagram, we must first understand the four modes of spi, and different modes collect data in different ways.
Generally, on the single-chip microcomputer with built-in SPI function, there are two register configuration bits CPOL and CPHA.
Let's take the STM32 microcontroller as an example, which can be configured through structure members.
This is directly configured through the firmware library, and the underlying code of the firmware library is also used to configure the corresponding registers.
Let's introduce what CPOL and CPHA are useful for.
CPOL is to determine the level state of the clock signal line SCLK when there is no data transmission.
CPOL=0: In idle state, SCLK remains low
CPOL=1: In idle state, SCLK keeps high level
CPHA is to determine whether the data bit transmission starts from the first clock (SCLK) edge, or the second from the second clock (SCLK) edge.
CPHA=0: Data is collected from the first clock (SLCK) edge
CPHA=1: Data is collected from the edge of the second clock (SLCK)
Ok, after understanding the basic concepts of CPOL and CPHA, the following two will start to "combine".
The combination of CPOL and CPHA forms the four modes of SPI.
Disclaimer: Some pictures are from the Internet and are not original.
Let's analyze the difference between the four modes, which is more important.
Because the slave, the slave refers to the chip that uses the SPI protocol to communicate, such as w25q64 (Flash) chip, OLED screen and so on.
Many slaves do not have CPOL and CPHA register setting bits. If you look at their data sheets, you will be confused, and you can't find these two things at all.
These all need to look at their timing diagrams to analyze what mode is used. If the mode is wrong, there will be problems with data transmission.
This is why it is possible to use the timing sequence written by myself on this chip, but not to switch to other spi communication chips.
1. Mode 0 (CPOL=0, CPHA=0)
Mode 0 Features:
CPOL = 0: low level when idle, the first transition edge is the rising edge, and the second transition edge is the falling edge
CPHA = 0: Data is sampled on the first transition edge (rising edge)
2. Mode 1 (CPOL=0, CPHA=1)
Mode 1 Features:
CPOL = 0: low level when idle, the first transition edge is the rising edge, and the second transition edge is the falling edge
CPHA = 1: Data is sampled on the second transition edge (falling edge)
3. Mode 2 (CPOL=1, CPHA=0)
CPOL = 1: High level when idle, the first transition edge is a falling edge, and the second transition edge is a rising edge
CPHA = 0: Data is sampled on the first transition edge (falling edge)
4. Mode 3 (CPOL=1, CPHA=1)
CPOL = 1: High level when idle, the first transition edge is a falling edge, and the second transition edge is a rising edge
CPHA = 1: Data is sampled on the second transition edge (rising edge)
I don’t know if you have discovered that the different modes are actually the difference between the level state of the SCLK idle time and the starting point of data sampling.
Are you useless? At the beginning, I was confused by these modes.
If you don’t understand, continue to read from the beginning. These 4 modes are the premise of analyzing the overall timing diagram later.
2. Detailed explanation of spi timing diagram
Congratulations here, you will be able to completely break the SPI protocol immediately.
Spi timing diagram, the best way is to learn through practical application.
Let's take the W25Q64 Flash chip as an example. This chip acts as a slave in SPI communication, that is, SPI Slave.
Generally, a single-chip microcomputer or other processor is used as the master to communicate with it, and the SLCK clock is also sent by the master.
The following is the timing diagram of the W25Q64 read data command, we use this example to explain how to look at the timing diagram.
1. First determine which SPI and which mode the chip supports to read and write data
After determining which mode to use, the master control, that is, the single-chip microcomputer, can determine the data collection method, and the master control and slave must be consistent.
From the timing diagram, it is not difficult to find that the data sheet of W25Q64 directly tells you that it supports SPI mode 0 and mode 3 for communication.
The data sheets of some chips do not tell you, so how do you know which mode to use?
Step 1: Analyze the level state of CLK when it is idle through the timing diagram. From the timing diagram above, we can know that both high and low levels are okay, right? Then we will continue to analyze it with the state that CLK is low when it is idle.
Step 2: Analyze whether DI and DO collect data on the rising or falling edge of CLK. Note that DI represents the MISO pin of the slave (W25Q64), and DO represents the MOSI pin of the slave (W25Q64).
We mainly judge whether CLK is rising or falling when DI and DO are in the data valid area.
What is the data valid area?
Look at the picture above, the area I framed in red is the valid data area.
Generally, the data is transmitted through the two pins of DI and DO, so the valid area of the data is that at this moment, the two pins can only be at a stable high level or low level.
The level equivalent to the effective data area is the final data bit to be transmitted, the low level represents 0, and the high level represents 1 .
8 bits are transmitted, representing 1 byte of data.
What is an invalid data area?
For example, the area of the blue box in the above figure is the invalid data area. It is at this moment that the CLK data acquisition clock has not come yet, so the levels of the DI and DO pins can be changed arbitrarily.
After understanding these two concepts, we need to focus on whether CLK is rising or falling when DI and DO are in the data valid area .
It can be seen from the above figure that when DI and DO are in the valid data area, CLK is on the rising edge, and on the falling edge, DI and DO are in the invalid data area where the level can be changed arbitrarily.
In this way, patterns can be analyzed.
Firstly, the data is collected on the rising edge, and through the exclusion method, only mode 0 and mode 3 meet the conditions.
Then the CLK idle time must be low, so that only mode 0 conforms.
Therefore, after knowing that mode 0 is used, the program written on the MCU will know whether the data is read from the rising edge of CLK, or sent, or from the falling edge.
2. Analyze the overall timing
To analyze timing, we must first be familiar with what function this timing needs to achieve. Although different functions have different timings, the order and definition of sending data are different.
The timing we are analyzing now is to read the stored data from the W25Q64 Flash chip.
I split the whole timing into 3 parts according to the CLK pulse sequence :
① Read command
It should be noted here that the read instruction data is generated at the DI pin of W25Q64, and DI is equivalent to MISO of W25Q64, which is to receive the data sent by the master control (usually a single-chip microcomputer).
Therefore, this read command (0x03) is sent by the MCU to W25Q64 .
0x03 is split into 8 bits and transmitted on the DI line, and 1 bit is transmitted on each rising edge of CLK.
②24-bit address
After sending the read command, the MCU continues to send the 24-bit memory address, which is equivalent to reading the data of which memory address of W25Q64.
This data is determined by the MCU program, so it is not fixed. You can see that the data bits can be high or low.
③MCU receives data
At this time, the roles of the communication parties have changed, the MCU has become the data receiver, and the W25Q64 has become the data sender.
Because the data is sent from the DO of W25Q64, which is the MOSI pin of W25Q64.
Through this sequence, the microcontroller can read the data stored in the address specified by W25Q64.
If you are a student of our Wuji single-chip computer programming, if you don’t understand the article well, you can give me feedback. If there are too many people who give feedback, we will explain it live. If there are few people, we will explain it one-on-one.
3. MCU program attention
51 microcontrollers generally do not have a built-in SPI module, so the entire timing needs to be simulated by writing a program, referred to as simulated SPI.
The STM32 microcontroller generally has a built-in SPI, so there is no need to write a program to simulate the timing and apply it directly.
But if you use the built-in SPI, there is a detail that is particularly easy to be ignored, that is, when you read data, you must send a byte of arbitrary value data before reading a byte.
Sending a byte of arbitrary value data is to generate a clock on the CLK bus to provide a clock for the SPI signal of the slave, and the SPI of the slave will not generate the CLK signal by itself.
For example, I have the following read data function:
If you can understand this step, you have basically understood the SPI protocol.
No matter how the slave is changed, for example, instead of W25Q24, it is replaced with an OLED screen, the timing principle is the same, but the related instructions and registers are different.
If it is helpful to you, please arrange a three-party party for me~