Based on Feiling's development board design, the serial port of RK3568 needs to be used here. The development board only opens UART2, UART3, UART4, UART5, and UART8. Check the documentation and prepare to configure UART0, UART6, UART7, and UART9. A total of 9 serial ports are used. The remaining serial port is occupied by network port 1 and will not be modified for the time being.
Modify the device tree DTS file configuration.
address:
/home/forlinx/3568/OK3568-linux-source/kernel/arch/arm64/boot/dts/rockchip
rk3568.dtsi is the basic configuration file, only OK3568-C-common.dtsi needs to be modified.
The LVDS pins are occupied and the LVDS cannot be used.
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/input/rk-input.h>
#include <dt-bindings/display/drm_mipi_dsi.h>
#include <dt-bindings/display/rockchip_vop.h>
#include <dt-bindings/display/media-bus-format.h>
#include "rk3568.dtsi"
/ {
model = "Forlinx OK3568-C Board";
compatible = "forlinx,ok3568", "rockchip,rk3568-evb1-ddr4-v10", "rockchip,rk3568";
//only hdmi
forlinx_control {
status = "okay";
video-hdmi = "hdmi";
video-mipi-edp = "off";
video-lvds = "off";
};
edp-panel {
compatible = "simple-panel";
prepare-delay-ms = <120>;
enable-delay-ms = <120>;
unprepare-delay-ms = <120>;
disable-delay-ms = <120>;
backlight = <&edp_backlight>;
enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};
panel {
compatible = "simple-panel";
backlight = <&lvds_backlight>;
power-supply = <&vcc3v3_lcd2_n>;
enable-delay-ms = <20>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
width-mm = <152>;
height-mm = <91>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <71000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <10>;
hfront-porch = <140>;
vback-porch = <1>;
vfront-porch = <2>;
hsync-len = <10>;
vsync-len = <20>;
hsync-active = <0>;
vsync-active = <1>;
de-active = <1>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dual-lvds-even-pixels;
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
};
};
};
};
adc_keys: adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
vol-up-key {
label = "volume up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <1750>;
};
vol-down-key {
label = "volume down";
linux,code = <KEY_VOLUMEDOWN>;
press-threshold-microvolt = <297500>;
};
menu-key {
label = "menu";
linux,code = <KEY_MENU>;
press-threshold-microvolt = <980000>;
};
back-key {
label = "back";
linux,code = <KEY_BACK>;
press-threshold-microvolt = <1305500>;
};
};
leds: leds {
compatible = "gpio-leds";
work_led: work {
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
hdmi_sound: hdmi-sound {
status = "okay";
compatible = "rockchip,hdmi";
rockchip,mclk-fs = <128>;
rockchip,card-name = "rockchip,hdmi";
rockchip,cpu = <&i2s0_8ch>;
rockchip,codec = <&hdmi>;
rockchip,jack-det;
};
pdmics: dummy-codec {
status = "disabled";
compatible = "rockchip,dummy-codec";
#sound-dai-cells = <0>;
};
pdm_mic_array: pdm-mic-array {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,name = "rockchip,pdm-mic-array";
simple-audio-card,cpu {
sound-dai = <&pdm>;
};
simple-audio-card,codec {
sound-dai = <&pdmics>;
};
};
audiopwmout_diff: audiopwmout-diff {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "rockchip,audiopwmout-diff";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,bitclock-master = <&master>;
simple-audio-card,frame-master = <&master>;
simple-audio-card,cpu {
sound-dai = <&i2s3_2ch>;
};
master: simple-audio-card,codec {
sound-dai = <&dig_acodec>;
};
};
rk809_sound: rk809-sound {
status = "okay";
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "rockchip,rk809-codec";
simple-audio-card,hp-det-gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
simple-audio-card,widgets = "Headphones", "Headphones Jack";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s1_8ch>;
};
simple-audio-card,codec {
sound-dai = <&rk809_codec>;
};
};
spdif-sound {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,name = "ROCKCHIP,SPDIF";
simple-audio-card,cpu {
sound-dai = <&spdif_8ch>;
};
simple-audio-card,codec {
sound-dai = <&spdif_out>;
};
};
spdif_out: spdif-out {
status = "disabled";
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
vcc12v: vcc-12v {
compatible = "regulator-fixed";
regulator-name = "vcc12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v>;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
//for main board
vcc3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc3v3>;
};
vcc1v2: vcc-1v2 {
compatible = "regulator-fixed";
regulator-name = "vcc1v2";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&vcc3v3>;
};
vcc2v8: vcc-2v8 {
compatible = "regulator-fixed";
regulator-name = "vcc2v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
vin-supply = <&vcc3v3>;
};
vcc3v3_lcd2_n: vcc3v3-lcd2-n {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_lcd2_n";
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc3v3_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
post-power-on-delay-ms = <200>;
reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
};
vcc2v5_sys: vcc2v5-ddr {
compatible = "regulator-fixed";
regulator-name = "vcc2v5-sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
vin-supply = <&vcc3v3_sys>;
};
5g-rst {
compatible = "regulator-fixed";
regulator-name = "5g-rst";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
enable-active-low;
regulator-boot-on;
regulator-always-on;
pinctrl-names = "default";
pinctrl-0 = <&net_5g_rst_gpio>;
status = "okay";
};
5g-pwr {
compatible = "regulator-fixed";
regulator-name = "5g-pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
regulator-always-on;
pinctrl-names = "default";
pinctrl-0 = <&net_5g_pwr_gpio>;
status = "okay";
};
fiq-debugger {
compatible = "rockchip,fiq-debugger";
rockchip,serial-id = <2>;
rockchip,wake-irq = <0>;
/* If enable uart uses irq instead of fiq */
rockchip,irq-mode-enable = <1>;
rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
debug: debug@fd904000 {
compatible = "rockchip,debug";
reg = <0x0 0xfd904000 0x0 0x1000>,
<0x0 0xfd905000 0x0 0x1000>,
<0x0 0xfd906000 0x0 0x1000>,
<0x0 0xfd907000 0x0 0x1000>;
};
cspmu: cspmu@fd90c000 {
compatible = "rockchip,cspmu";
reg = <0x0 0xfd90c000 0x0 0x1000>,
<0x0 0xfd90d000 0x0 0x1000>,
<0x0 0xfd90e000 0x0 0x1000>,
<0x0 0xfd90f000 0x0 0x1000>;
};
test-power {
status = "okay";
};
rk_headset: rk-headset {
status = "disabled";
compatible = "rockchip_headset";
headset_gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
io-channels = <&saradc 2>;
};
dsi1_backlight: dsi1-backlight {
compatible = "pwm-backlight";
pwms = <&pwm5 0 20000 0>;
brightness-levels = <
0 20 20 21 21 22 22 23
23 24 24 25 25 26 26 27
27 28 28 29 29 30 30 31
31 32 32 33 33 34 34 35
35 36 36 37 37 38 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255
>;
default-brightness-level = <200>;
is-forlinx;
};
lvds_backlight: lvds-backlight {
compatible = "pwm-backlight";
pwms = <&pwm14 0 20000 0>;
brightness-levels = <
0 20 20 21 21 22 22 23
23 24 24 25 25 26 26 27
27 28 28 29 29 30 30 31
31 32 32 33 33 34 34 35
35 36 36 37 37 38 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255
>;
default-brightness-level = <200>;
is-forlinx;
};
edp_backlight: edp-backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 20000 0>;
brightness-levels = <
0 20 20 21 21 22 22 23
23 24 24 25 25 26 26 27
27 28 28 29 29 30 30 31
31 32 32 33 33 34 34 35
35 36 36 37 37 38 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255
>;
default-brightness-level = <200>;
};
};
&reserved_memory {
ramoops: ramoops@110000 {
compatible = "ramoops";
reg = <0x0 0x110000 0x0 0xf0000>;
record-size = <0x20000>;
console-size = <0x80000>;
ftrace-size = <0x00000>;
pmsg-size = <0x50000>;
};
};
&rng {
status = "okay";
};
&rockchip_suspend {
status = "okay";
};
&combphy0_us {
status = "okay";
};
&combphy1_usq {
status = "okay";
};
&combphy2_psq {
status = "okay";
};
&csi2_dphy_hw {
status = "okay";
};
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ov13850: endpoint@1 {
reg = <1>;
remote-endpoint = <&ov13850_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&isp0_in>;
};
};
};
};
&gmac0 {
phy-mode = "rgmii";
clock_in_out = "output";
snps,reset-gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>, <25000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus
ð0_pins>;
tx_delay = <0x2f>;
rx_delay = <0x00>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
&gmac1 {
phy-mode = "rgmii";
clock_in_out = "output";
snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>, <25000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus
ð1m1_pins>;
tx_delay = <0x35>;
rx_delay = <0x00>;
phy-handle = <&rgmii_phy1>;
status = "okay";
};
&mdio0 {
rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
clocks = <&cru CLK_MAC0_OUT>;
};
};
&mdio1 {
rgmii_phy1: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
clocks = <&cru CLK_MAC1_OUT>;
};
};
&video_phy0 {
status = "disabled";
};
&video_phy1 {
status = "disabled";
};
/*
&pcie30phy {
status = "okay";
};
&pcie3x2 {
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_sys>;
status = "okay";
};
&pcie2x1 {
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_sys>;
status = "okay";
};
*/
&pinctrl {
touch {
touch_gpio: touch-gpio {
rockchip,pins =
<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
ft5x06_int: ft5x06-int {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
};
dsi_gt911_int: dsi-gt911-int {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
cam {
camera_pwr: camera-pwr {
rockchip,pins =
/* camera power en */
<0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
ov13850_default_pin: ov13850-default-pin {
rockchip,pins =
<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,
<0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
ov13850_sleep_pin: ov13850-sleep-pin {
rockchip,pins =
<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,
<0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
headphone {
hp_det: hp-det {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int: pmic_int {
rockchip,pins =
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
soc_slppin_gpio: soc_slppin_gpio {
rockchip,pins =
<0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>;
};
soc_slppin_slp: soc_slppin_slp {
rockchip,pins =
<0 RK_PA2 1 &pcfg_pull_up>;
};
soc_slppin_rst: soc_slppin_rst {
rockchip,pins =
<0 RK_PA2 2 &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
5g {
net_5g_rst_gpio: net_5g_rst_gpio {
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
net_5g_pwr_gpio: net_5g_pwr_gpio {
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&rkisp {
status = "okay";
};
&rkisp_mmu {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp0_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&csidphy_out>;
};
};
};
&sdmmc2 {
max-frequency = <150000000>;
supports-sdio;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
sd-uhs-sdr104;
status = "okay";
};
&uart8 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>;
};
&bus_npu {
bus-supply = <&vdd_logic>;
pvtm-supply = <&vdd_cpu>;
status = "okay";
};
&can0 {
assigned-clocks = <&cru CLK_CAN0>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&can0m0_pins>;
status = "okay";
};
&can1 {
assigned-clocks = <&cru CLK_CAN1>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&can1m1_pins>;
status = "okay";
};
&can2 {
assigned-clocks = <&cru CLK_CAN2>;
assigned-clock-rates = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&can2m1_pins>;
status = "disabled";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&dfi {
status = "okay";
};
&dmc {
center-supply = <&vdd_logic>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: tcs4525@1c {
compatible = "tcs,tcs452x";
reg = <0x1c>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "fan53555-reg";
regulator-name = "vdd_cpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1390000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <2300>;
fcs,suspend-voltage-selector = <1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
//fb-inner-reg-idxs = <2>;
/* 1: rst regs (default in codes), 0: rst the pmic */
pmic-reset-func = <0>;
/* not save the PMIC_POWER_EN register in uboot */
not-save-power-en = <1>;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
pwrkey {
status = "okay";
};
pinctrl_rk8xx: pinctrl_rk8xx {
gpio-controller;
#gpio-cells = <2>;
rk817_slppin_null: rk817_slppin_null {
pins = "gpio_slp";
function = "pin_fun0";
};
rk817_slppin_slp: rk817_slppin_slp {
pins = "gpio_slp";
function = "pin_fun1";
};
rk817_slppin_pwrdn: rk817_slppin_pwrdn {
pins = "gpio_slp";
function = "pin_fun2";
};
rk817_slppin_rst: rk817_slppin_rst {
pins = "gpio_slp";
function = "pin_fun3";
};
};
regulators {
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_logic";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_gpu";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_npu";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_image";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda_0v9";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_acodec";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca_1v8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_image";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_3v3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc3v3_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
rk809_codec: codec {
#sound-dai-cells = <0>;
compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
clocks = <&cru I2S1_MCLKOUT>;
clock-names = "mclk";
assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>;
assigned-clock-rates = <12288000>;
assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_mclk>;
hp-volume = <20>;
spk-volume = <3>;
mic-in-differential;
status = "okay";
};
};
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2m1_xfer>;
vm149c_0: vm149c@0c {
compatible = "silicon touch,vm149c";
status = "okay";
reg = <0x0c>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
};
ov13850: ov13850@10 {
compatible = "ovti,ov13850";
status = "okay";
reg = <0x10>;
clocks = <&cru CLK_CIF_OUT>;
clock-names = "xvclk";
power-domains = <&power RK3568_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&cif_clk>, <&ov13850_default_pin>;
pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "ov13850-csi";
rockchip,camera-module-lens-name = "ov13850-2mp";
lens-focus = <&vm149c_0>;
port {
ov13850_out: endpoint {
remote-endpoint = <&mipi_in_ov13850>;
data-lanes = <1 2>;
};
};
};
gt9xx_lvds: gt9xx@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&touch_gpio>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
irq-gpio = <&gpio1 RK_PA4 IRQ_TYPE_LEVEL_LOW>;
reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
touchscreen-size-x = <1280>;
touchscreen-size-y = <800>;
touchscreen-swapped-x-y;
uniq = "lvds";
status = "okay";
};
gt9xx_dsi: gt9xx@14 {
compatible = "goodix,gt928";
reg = <0x14>;
pinctrl-names = "default";
pinctrl-0 = <&dsi_gt911_int>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>;
irq-gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
reset-gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
touchscreen-size-x = <1024>;
touchscreen-size-y = <600>;
uniq = "dsi";
status = "okay";
};
polytouch: edt-ft5x06@38{
compatible = "edt,edt-ft5406", "edt,edt-ft5x06";
reg = <0x38>;
pinctrl-names = "defaults";
pinctrl-0 = <&ft5x06_int>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>;
touchscreen-size-x = <1024>;
touchscreen-size-y = <600>;
status = "okay";
};
};
&i2c3 {
status = "okay";
rx8010: rx8010@32 {
compatible = "epson,rx8010";
reg = <0x32>;
};
pcf8563: pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
#clock-cells = <0>;
};
};
&i2s0_8ch {
status = "okay";
};
&i2s1_8ch {
status = "okay";
rockchip,clk-trcm = <1>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_sclktx
&i2s1m0_lrcktx
&i2s1m0_sdi0
&i2s1m0_sdo0>;
};
&iep {
status = "okay";
};
&iep_mmu {
status = "okay";
};
&jpegd {
status = "okay";
};
&jpegd_mmu {
status = "okay";
};
&mpp_srv {
status = "okay";
};
&nandc0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
nand@0 {
reg = <0>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <16>;
nand-ecc-step-size = <1024>;
};
};
/*
* There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7].
* 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured;
* 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages
* must be consistent with the software configuration correspondingly
* a/ When the hardware IO level is connected to 1.8V, the software voltage configuration
* should also be configured to 1.8V accordingly;
* b/ When the hardware IO level is connected to 3.3V, the software voltage configuration
* should also be configured to 3.3V accordingly;
* 3/ VCCIO2 voltage control selection (0xFDC20140)
* BIT[0]: 0x0: from GPIO_0A7 (default)
* BIT[0]: 0x1: from GRF
* Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7:
* L:VCCIO2 must supply 3.3V
* H:VCCIO2 must supply 1.8V
*/
&pmu_io_domains {
status = "okay";
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>;
};
&pwm3 {
status = "okay";
};
&pwm5 {
status = "okay";
};
&pwm14 {
status = "disabled";
};
&rk_rga {
status = "okay";
};
&rkvdec {
status = "okay";
};
&rkvdec_mmu {
status = "okay";
};
&rkvenc {
venc-supply = <&vdd_logic>;
status = "okay";
};
&rkvenc_mmu {
status = "okay";
};
&rknpu {
rknpu-supply = <&vdd_npu>;
status = "okay";
};
&rknpu_mmu {
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vcca_1v8>;
};
&sdhci {
bus-width = <8>;
supports-emmc;
non-removable;
max-frequency = <200000000>;
status = "okay";
};
&sdmmc0 {
max-frequency = <150000000>;
supports-sd;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
//20220927 by gan
status = "disabled";
};
&sfc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&fspi_pins>;
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
m25p,fast-read;
};
};
&spdif_8ch {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&spdifm1_tx>;
};
&tsadc {
status = "okay";
};
&u2phy0_host {
status = "okay";
};
&u2phy0_otg {
status = "okay";
};
&u2phy1_host {
status = "okay";
};
&u2phy1_otg {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd_dwc3 {
dr_mode = "otg";
extcon = <&usb2phy0>;
status = "okay";
};
&usbdrd30 {
status = "okay";
};
&usbhost_dwc3 {
status = "okay";
};
&usbhost30 {
status = "okay";
};
&vad {
rockchip,audio-src = <&i2s1_8ch>;
rockchip,buffer-time-ms = <128>;
rockchip,det-channel = <0>;
rockchip,mode = <0>;
};
&vdpu {
status = "okay";
};
&vdpu_mmu {
status = "okay";
};
&vepu {
status = "okay";
};
&vepu_mmu {
status = "okay";
};
&vop {
status = "okay";
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>, <&cru PLL_GPLL>;
disable-win-move;
};
&vop_mmu {
status = "okay";
};
&vp0 {
cursor-win-id = <ROCKCHIP_VOP2_CLUSTER0>;
};
&vp1 {
cursor-win-id = <ROCKCHIP_VOP2_CLUSTER1>;
};
&edp {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&edpdpm0_pins>;
ports {
port@1 {
reg = <1>;
edp_out_panel: endpoint {
remote-endpoint = <&panel_in_edp>;
};
};
};
};
&edp_phy {
status = "disabled";
};
&edp_in_vp0 {
status = "disabled";
};
&edp_in_vp1 {
status = "disabled";
};
&route_edp {
status = "disabled";
connect = <&vp1_out_edp>;
};
&route_dsi1 {
status = "disabled";
connect = <&vp1_out_dsi1>;
};
&dsi1_in_vp0 {
status = "disabled";
};
&dsi1_in_vp1 {
status = "disabled";
};
&dsi1 {
status = "disabled";
//rockchip,lane-rate = <1000>;
dsi1_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
reset-delay-ms = <60>;
enable-delay-ms = <60>;
prepare-delay-ms = <60>;
unprepare-delay-ms = <60>;
disable-delay-ms = <60>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
];
panel-exit-sequence = [
];
panel-width-mm = <68>;
panel-height-mm = <121>;
backlight = <&dsi1_backlight>;
enable-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
display-timings {
native-mode = <&panel7_1024x600>;
panel7_1024x600: timings {
hback-porch = <48>;
hfront-porch = <40>;
hactive = <1024>;
hsync-len = <48>;
vback-porch = <48>;
vfront-porch = <40>;
vactive = <600>;
vsync-len = <4>;
clock-frequency = <45000000>;
vsync-active = <0>;
hsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi: endpoint {
remote-endpoint = <&dsi_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi>;
};
};
};
};
&hdmi {
status = "disabled";
rockchip,phy-table =
<92812500 0x8009 0x0000 0x0270>,
<165000000 0x800b 0x0000 0x026d>,
<185625000 0x800b 0x0000 0x01ed>,
<297000000 0x800b 0x0000 0x01ad>,
<594000000 0x8029 0x0000 0x0088>,
<000000000 0x0000 0x0000 0x0000>;
};
&hdmi_in_vp0 {
status = "disabled";
};
&hdmi_in_vp1 {
status = "disabled";
};
&route_hdmi {
status = "disabled";
connect = <&vp0_out_hdmi>;
};
&lvds {
status = "disabled";
phys = <&video_phy0>;
phy-names = "phy";
ports {
port@1 {
reg = <1>;
lvds_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
&lvds_in_vp1 {
status = "disabled";
};
&lvds_in_vp2 {
status = "disabled";
};
&route_lvds {
status = "disabled";
connect = <&vp2_out_lvds>;
};
&xin32k {
status = "disabled";
};
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart3m1_xfer>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart4m1_xfer>;
};
&uart5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart5m1_xfer>;
};
/
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
};
&uart6 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart6m1_xfer>;
};
&uart7 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart7m1_xfer>;
};
&uart9 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart9m1_xfer>;
};
//
&spi0 {
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi0m1_cs0 &spi0m1_pins>;
pinctrl-1 = <&spi0m1_cs0 &spi0m1_pins_hs>;
status = "disabled";
spi@0 {
compatible = "rockchip,spidev";
reg = <0>;
spi-max-frequency = <50000000>;
};
};
&spi2 {
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins>;
pinctrl-1 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins_hs>;
status = "okay";
spi@0 {
compatible = "rockchip,spidev";
reg = <0>;
spi-max-frequency = <50000000>;
};
spi@1 {
compatible = "rockchip,spidev";
reg = <1>;
spi-max-frequency = <50000000>;
};
};
After compilation, burn the boot file and test the serial port communication successfully.