Synopsys training lab1

Experiment 1 mainly has several tasks on interfaces and their instantiation.

Task 1: Create interfaces for these signal ports and define clock blocks for them. The always block is required to be driven on the rising edge of the clock, and add port connections between the test program and the DUT. All directions are required to be relative to the test program. ,In addition, modport must be used in the interface to indicate that reset_n is output.

interface router_io(input bit clk);
//创建接口，没有指明方向
logic 			reset_n		,
logic	[15:0]	din			,
logic 	[15:0]	frame_n		,
logic 	[15:0]	valid_n 	,
logic 	[15:0]	dout 		,
logic	[15:0]	frameo_n	,
logic 	[15:0]	valido_n	,
logic 	[15:0]	busy_n		;

//创建时钟块
//相对于testprogram，再testgram中，router的输入就是我们
//的激励输出，而router的输出就是我们的输入，此时要验证
//功能是否正确
clocking cb @(posedge clk);
default input #1ns output #1ns;
    output reset_n;
	output din;
	output frame_n;
	output valid_n;
	input  dout;
	input  valido_n;
	input  frameo_n;
	input  busy_n;
endclocking:cb

//声明modport
modport TB(clocking cb, output reset_n);
endinterface

Task 2: 1. Declare a program block and connect it to the modport TB declared in the interface. 2. In the Initial statement block, print a simple message to the screen.

//声明program块
program automatic test(router_io.TB rtr_io);
  initial begin
  //打印信息
    $display("This is lab1");
	reset();
  end
//写复位任务，即一些初始化工作
task reset();
  rtr_io.reset_n = 1'b0;
  rtr_io.cb.frame_n <= '1;
  rtr_io.cb.valid_n <= '1;
  ##2 rtr_io.cb.reset_n <= 1'b1;
  repeat(15) @(rtr_io.cb);
endtask: reset
endprogram:test

Task 3: Connect the test program and DUT through inteface

`timescale 1ns/100ps

module router_test_top;
  parameter simulation_cycle = 100;

  bit SystemClock;
  //添加接口实例                                                                                                                                                                                                                                  
  router_io top_io(SystemClock);
  //实例化test program
  //通过接口实现IO连接
  test t(top_io); 
  //实例化dut
  //端口名可以由interface_name.signal_name来表示
  router dut(
    .reset_n	(top_io.reset_n),
    .clock		(top_io.clock),
    .din		(top_io.din),
    .frame_n	(top_io.frame_n),
    .valid_n	(top_io.valid_n),
    .dout		(top_io.dout),
    .valido_n	(top_io.valido_n),
    .busy_n		(top_io.busy_n),
    .frameo_n	(top_io.frameo_n)
  );
   //初始化语句块
  initial begin
  	//添加时间格式
	$timeformat(-9, 1, "ns", 10);
    SystemClock = 0;
    forever begin
      #(simulation_cycle/2)
        SystemClock = ~SystemClock; //时钟信号产生
    end
  end

endmodule