brief introduction
Raspberry Pi single-board computers (Raspberry Pi Single Computer) is a very great product, users can get a very low cost Linux environment with GPIO and hardware extensions mini computer system. Raspberry Pi 4B also offers a new generation of good things and AIoT industrial support. Raspberry Pi single-board computer has a complete ecological chain, hardware and software is rich in resources, it is a good choice for embedded systems development and intelligent hardware product innovation.
As the basis for embedded systems and embedded intelligent hardware development foundation, the assembly language is a lot of information in science and engineering and technical personnel should have a basic skills. At present, the resource description language and practice of programming C, Scratch, Python, etc. on the market for Raspberry Pi single-board computer system are many, but few systematic compilation introduce programming language for Raspberry Pi single-board computer ARM. Here at Yuan Zhiyong editor of the "Principles and Applications of Embedded Systems Technology" (Beijing University of Aeronautics and Astronautics Press January 2019 3rd edition) book ARM assembly language programming knowledge basis using the Raspberry Pi single-board computer and the Linux operating system verification platform, a more systematic introduction raspberry Pi ARM assembly language programming techniques and examples. Due to short notice, so inappropriate, also please let me know.
Lecture 3: ARM instruction addressing and stack addressing Raspberry Pi ARM assembler Examples
Lecture 3 Contents
· ARM instruction format and classification
· ARM instruction addressing modes
· Stack addressing ARM assembler example
Use GNU GDB debugger command stack addressing ARM assembler and observation Raspberry Pi memory stack memory
a, ARM instruction classification format and
ARM instruction set is embedded microprocessor load, store-type, i.e. the data processing instruction set can only register, and the processing result to be written back to the register, the memory is accessed through a special loading required, store instruction to complete. ARM instructions can be divided into the following six categories:
● Data processing instructions: data transfer instructions, arithmetic instructions, logical instructions, comparison instructions, multiply instructions, leading zero count
● program status access instructions: the MRS and the MSR
● branch instructions: B, BL, and BX
● memory access instructions: single data memory access instruction, multiple-data memory access instruction, the data exchange instruction
● generation instruction exception: the SWI and BKPT
● coprocessor instructions: CDP, LDC, STC, MCR , MRC
herein by ARM-based data processing instructions to illustrate the ARM instruction format. ARM-based data processing instruction encoding basic format as shown in FIG.
1 ARM data processing class FIG instruction encoding format
GNU ARM data processing instructions assembly statement basic format is as follows:
{label:} [Opcode] {cond} {s} [Rd], [Rn], [Operand2] {@ Notes}
wherein, items in [] is necessary, in terms {} are optional. If so the instruction mnemonic, is necessary, but is {cond} instruction execution conditions, it is optional, if the default conditions do not write AL (unconditional execution).
● cond: condition indicates execution instruction / condition code;
● Opcode: instruction mnemonic indicates / operation code (there are 16 code, corresponding to the data processing instruction 16);
● S: indicates whether the instruction operation affect CPSR, S suffixes when no operation instruction does not update the CPSR condition flags;
● Rn of: represents a register of the first operand, or coding;
● Rd: indicates the destination register or a coding;
● of Operand2: represents the second operand, the second operand may be immediate, register, register displacement;
● X-: =. 1 shows a second X-operand is immediate addressing; X = 0 represents the second operand is a register addressing.
, The Opcode Operation code (not included multiply instruction) corresponding to the instruction mnemonics according to the coding format shown in FIG. 1 and their meanings are as follows:
0000: the AND, the AND Rd ← Op1 Op2
0001: the EOR, the EOR Rd ← Op1 Op2
0010: the SUB, Rd ← Op1-Op2
0011: the RSB, Rd ← Op2-Op1
0100: the ADD, Rd ← Op1 + Op2
0101: the ADC, Rd ← Op1 + Op2 + C
0110: the SBC, Rd ← OP1-Op2 + C-. 1
0111 : the RSC, Rd ← Op2-Op1 + C-. 1
1000: the TST, set Op1 AND Op2 condition code
1001: TEQ, home OP1 EOR Op2 condition code
1010: CMP, set Op1-Op2 condition code
1011: CMN, set Op1 + Op2 condition code
1100: ORR, Rd ← Op1 OR Op2
1101: MOV, Rd ← Op2
1110: BIC, the NOT the AND Rd ← Op1 Op2
1111: MVN, the NOT Op2 Rd ←
bits and the position of the condition code: each comprising four ARM instruction condition code field, which occupies the highest encoded with instructions 4 [31:28].
Condition code indicates: the conditions of 24 = 16 kinds of encoding, wherein the 15 kinds of the condition code for the instruction. Each condition code indicates (see Table 1) with two abbreviation characters.
Conditional execution instructions: ARM processor instruction according to the execution condition is satisfied, it determines whether the current instruction execution. Only in the CPSR condition flags specified conditions are met, the instruction will be executed. Ineligible code is still occupied by one clock cycle (equivalent to a NOP instruction).
Code writing process conditions: the position of the condition code after the instruction mnemonic (therefore also referred to as conditions suffix).
Example: MOVEQ R0, R1
Table 1 ARM instruction condition code
two, ARM instruction addressing mode
called the processor addressing mode is to find the physical address of the operand from the address information of the instruction given manner. Currently ARM processor supports several common addressing.
1. Register Addressing
Register Addressing refers to a desired value in a register, the instruction is given in the address code register number, i.e., the contents of the register as an operand.
Example. 1:
the ADD R0, Rl, R2 R0 @ Rl + R2 ←
2. Now addressing
immediate addressing is a special addressing mode, the instruction address code is not part of an operand address on the back of the operation code field, but operand itself.
Example 2:
the ADD R3, R3, R3 ← # R3 + 10 @ 10
To literal "#" is prefixed to the decimal number 10 for example, the hexadecimal number immediately # 0xa, 2 decimal immediately # 0b1010.
Number of constituting an immediate, refer to FIG. 2.
FIG 2 a schematic configuration immediate
seen from FIG. 3.2, effective immediate can be expressed as: = Immed_8 Rotate Right rot × 2 bits
as the values of four rot shift values (0 15) is multiplied by 2, to give a range of 0 30. the step size is a shift value of 2. Thus, in the immediate ARM yet 8-bit in FIG. We only need to remember a rule: "The last eight Immed_8 move even bits" to get the number right away. Only through this constructor get immediate is legal.
The following are three with corresponding machine code MOV instruction and immediate data, please note that the number of machine code calculation:
MOV R0, # 0xF200
@ E3A00CF2, 0xF200 0xF2 = Rotate Right (2 × C)
MOV Rl, # 0x110000
@ E3A01811, 0x110000 = 0x11 rotate right (2 ×. 8)
MOV R4, 0x12800 #
@ E3A04B4A, 0x12800 = 0x4A rotate right (2 × B)
In another example, 0xFF, 0x104 (8 which Pictured 0x41), 0xFF0, 0xFF00 is legitimate immediate; 0x101,0x102,0xFF1 is illegal immediate.
3. Register Addressing shift
register is shifted addressing specific ARM instruction set, the second operand registers before combining with the first operand, select shift operation. In addressing the shift register, the shift bits can be represented by the number of registers or immediate mode.
Example 3:
ADD R3, R2, R1, LSL # 3 @ R3 ← R2 + 8 × R1 ( i.e., R1 is the value to the left by 3 bits and added to the value in R2 and stores the result R3)
MOV R0, R1, R2 ROR Rotate right @ R0 ← R1 R2 bit
ARM has a barrel shifter, via its operand to be shifted or rotated any number of bits before being used, in which the processing lists, tables, and other complex data structures when very useful.
Some commonly used ARM instruction shift operation as follows:
(1) ASR Arithmetic shift right
number register storing a second arithmetic shift right operation. Arithmetic shift operand is signed numbers, symbols should remain constant operand shift completion. Thus, when the operation is shifted to the number of positive, high-bit register vacated complement 0; when the operand to be shifted is negative, register empty bit high S.1.
(2) LSL logic shift left
register storing a second number of logical left shift operation. End to the C register flag, low vacated bit 0s.
(3) LSR Logical shift right
registers storing a second number of logical shift right operation. High register vacated bit 0s.
(4) ROR Rotate Right
number register storing the second operation cycle right. Fill out the lower end of the bit from the register to the end of the vacated bit register.
(5) Rotate Right RRX extended
cycle the second operand is stored into the register bit to the right. Every right shift, register empty bit high filling value of the original C flag.
If the number of bits shifted by a 5-bit immediate (range 0-31) is given, the control number is called the shift mode (immediate specified shift) immediately; if the number of bits shifted by the general-purpose register (not a R15) 5 low decision, called mode control shift register (register specified shift).
About control shift register mode, the following points should be noted:
● shift register can not be a PC, or will cause unpredictable results.
● using the control shift register mode additional consideration (overhead), require more instruction cycles to complete, because the ARM not afford to read three registers.
Number of control shift mode immediately there is no such problem.
4. Register Indirect
Register Indirect addressing instruction address code is given a number of general purpose registers, the effective address of the operand is stored in the designated register, and the operand is stored at the address corresponding to storage unit, i.e., a register address pointer.
Example. 4: the LDR R0, [Rl] @ R0 ← [Rl]
5. The indexed addressing yl
group indexed addressing (or simply indexed addressing) is to command base register contents given in adding an offset to form the effective address operand. Close access to the base address indexed addressing unit, comprising base address plus offset and the base address indexed addressing. Register indirect addressing is offset 0 base address plus offset addressing.
Base-plus-displacement addressing base address register contains the address is not exact. Need to add a base address to compute the address accessed (or minus) the maximum offset of 4KB.
Example 5: LDR R0, [R1, # 4] @ R0 ← [R1 + 4]
Three plus an offset (offset address) in the indexed addressing mode:
(1) before addressing mode (pre-indexed)
first base address plus an offset, to generate an operand address specified by the instruction operations do. This embodiment does not modify the base register. As, i.e., the above example for this embodiment.
(2) automatic addressing mode (auto-indexed)
first base address plus an offset, to generate an operand address specified by the instruction operation do; then automatically modified base register.
Example 6: LDR R0, [R1, # 4] @ R0 ← [R1 + 4], R1 ← R1 + 4!
Description:! It represents a write-back or update the base register.
(3) addressing mode (post-indexed)
First base register as an operand address; After completion of the operation command, then the base address plus offset modify the base register. I.e. first with the base address of data transmission, and then modify the base address (base + offset).
Example 7: STR R0, [R1] , # 12 @ [R1] ← R0, R1 ← R1 + 12
where R1 is a base register.
6. Relative addressing
Relative addressing is a workaround indexed addressing, the base address provided by the program counter the PC, the address field of the instruction code as an offset, both the effective address of the operand after the addition. Offset noted that the relative position between the current instruction operand. I.e., the subroutine call instruction is a BL instruction relative addressing.
Example. 8:
BL ROUTE_A @ subroutine call ROUTE_A
BEQ LOOP @ conditional jump to the label LOOP
...
LOOP: MOV R2, # 2
...
ROUTE_A: ...
7. The multi-register addressing
multiple register addressing means is a plurality of instructions can be completed transfer register value. This addressing mode allows the instruction to complete the transfer up to a value of 16 general registers.
● Multi-register addressing is the use of a plurality of register transfer instruction LDM / STM addressing modes;
● Multi-register transfer instructions to transfer data to a memory from a location to another location;
● addressing operation multi-register instruction is above or below depending on the data stored in the base register address indicated above, the address is incremented or decremented, and the data related to the access operation;
● multi-register addressing operation registers, which may be R0 ~ R15 subset of registers 16, or all the registers.
Several multi-register instruction and the addressing operation as follows:
LDMIA / STMIA.: First transmission, the address plus 4 (the After Increment);
LDMIB / STMIB: first address plus 4, after the transfer (the Before Increment);
LDMDA / STMDA: first transmission, the address minus 4 (of Decrement the after);
LDMDB / of STMDB: Save first address 4, after the transfer (Decrement before).
Example. 9:
LDMIA R1, {R0, R2, R5} @ R0 ← [R1], R2 ← [R1 +. 4], R5 ← [R1 +. 8]
meanings indicated above instruction is to R1 pointed three consecutive memory cells contents are supplied to the register R0, R2, R5 in.
Since the transfer of the data item is always 32-bit word, the word should be aligned with the base address of R1.
Example 10:
STMIA. R10, {r0 of, R1, R4}
STMIB R10, {r0 of, R1, R4}
STMDA R10, {r0 of, R1, R4}
of STMDB R10, {r0 of, R1, R4}
The above operation executed by four instructions as shown in Figure 3.
Figure 3 a schematic view of a multi-register addressing
8. Stack addressing
stack is a storing area accessed in a particular order, this particular sequence that is "last out" or "last in, first out." Stack addressing is implied, which uses a dedicated register (stack pointer) points to a memory area. The stack pointer is specified by the storage unit to stack top. Stack can be divided into two types:
● grown up: also known increments (Ascending) stack, i.e., the higher addresses address growth.
● Down Growth: also known decremented (Descending) stack, i.e., the address to the low address growth direction.
If the SP points to the last valid data unit is pushed into the stack, the stack is called a full (Full Stack); SP points to an empty cell if the next data item into a called empty stack (Empty stack).
ARM processor supports four types of stacks above work:
● a full stack is incremented FA (Full Ascending): the stack pointer into a data unit last nip, and generated from low to higher addresses;
● a full descending stack FD (Full Descending ): stack pointer points to a data unit last pushed in, and generated by the high address to the lower address;
● space increment stack EA (empty Ascending): stack pointer points to be placed in the empty cell data, and from low addresses to high address generation;
● empty decrements the stack ED (empty Descending): under the stack pointer to be placed in an empty cell data, and an address generated by the high to the low address;
Example. 11:
STMFD SP !, {R4-R7, LR @} the r4 ~ r7, lr stack full descending stack
LDMFD sp !, {r4-r7, pc} @ the stack is placed r4 ~ r7, pc register
4 stack operations schematic
Figure 4 illustrates this embodiment two instructions the push and pop operations process, the left end of FIG STMFD incoming operation, the right end of FIG LDMFD pop operation. It should be noted that, when using a full descending stack, STMFD STMDB instruction corresponding to the instruction, LDMFD LDMIA instruction corresponding to the instruction. STMFD / LDMFD ARM is the most common mode of operation the stack, the stack address with multiple addressing control register shown in Table 2.
Table 2 Multi-Stack addressing and control register addressing
three, ARM assembler Stack addressing Examples
The following Example 11 to stack manipulation instructions given on the basis of a complete stack addressing ARM assembler, ARM source program list, see the following:
@filename: stackaddressing.s
.global _start @ global declaration numeral _start
_start: LDR the SP, = 0x7EFFF150
MOV the LR, # 0x8034
MOV R4, # 0x0100
MOV R5, # 0x00FF
MOV R6, # 0x1234
MOV R7, # 0xA0BE
STMFD the SP!, {R4-R7, the LR}
LDMFD the SP!, {R0-R3, R9}
B _start
.end
function of the program is started, a pointer to set the SP raspberry Pi as a stack memory address 0x7EFFF150 bottom of the stack (due to different systems use different raspberry Pi scenarios, it is recommended to use the default stack, and the program of a can be omitted), then 5 transfer instruction MOV sequence of statements are to LR, R4-R7 register initial value. The last two registers are pushed and popped, it is known from STMFD / LDMFD instruction, where the assembler program uses a full descending stack for stack operations.
Fourth, the use GNU GDB debugger command ARM assembler Stack addressing memory and send the Observation raspberry stack memory
after the operation performed Raspberry Pi Linux terminal stack, Stack addressing ARM assembler, GNU GDB observed likewise be sent memory raspberry stack area. This stresses Stack addressing ARM assembler example using GNU GDB command as follows:
(. 1) L (IST): line numbers displayed ARM assembler source
(2) b (reak): Set interrupt ARM assembler source program executed block number (i.e., set breakpoints)
(3) run: Run the program and the next breakpoint pause
(4) i (nfo): Display all the ARM register or break ® (B)
(. 5) S (TEP): Single-step next instruction
(6 ) x / nx addr: the address unit "addr", beginning with the hexadecimal format content of n word units
(7) q (uit): exit and return GDB debugger command status Linux command prompt the terminal to send raspberry
first editing stackaddressing.s named ARM assembler using nano editor (see FIG. 5).
5 Edit Stack addressing Raspberry Pi ARM assembler source
Then, in the Raspberry Pi Linux terminal command prompt, enter the command sequence called stackaddressing.s source code to compile, link, execute GDB stackaddressing command to enter the GDB debugger command state (see FIG. 6).
FIG 6 performs GDB stackaddressing command, enter debug state GDB commands
display list commands ARM assembler source line numbers (see FIG. 7).
7 l with the command line numbers displayed ARM assembler source
with the command to set a breakpoint b 9 to the line 9 stmfd SP, {R4-R7, LR} statement;! Statement executes a program in the run command to line 9 stopped at display line and the statement of the breakpoint; ARM register contents inside the display command by ir, with x / 10x 0x7efff13c raspberry command displays the contents sent from the stack area of RAM starting address unit 0x7efff13c word units 10 (see FIG. 8).
Figure 8 shows the contents of an ARM register and a RAM value of the stack area raspberry pie
seen from FIG. 8, line 9 to the program execution at the breakpoint, sp = 0x7efff150, r4 = 0x100 , r5 = 0xff, r6 = 0x1234, r7 = 0xa0be.
S command input following single-step push instruction then executes stmfd line 9 (see FIG. 9).
Figure 9 shows the contents of ARM register value and send raspberry RAM stack area after the execution of the instruction stack stmfd
in FIG. 9, again using the display register ir command value, using the x / 10x 0x7efff13c raspberry send commands display RAM stack area 0x7efff13c SUMMARY unit 10 starts the word units.
Push instruction stmfd SP !, {R4-R7, LR} in the implementation of Figure 10 Raspberry Pi FIG.
FIG 10 push instruction stmfd SP !, {R4-R7, LR} implementation of raspberry send
stmfd SP !, {R4-R7, LR} micro instruction corresponding push operation sequence is as follows:
the SP-the SP. 4 ← , [the SP] ← the LR
the SP ← the SP-. 4, [the SP] ← R7
the SP ← the SP-. 4, [the SP] ← R6
the SP ← the SP-. 4, [the SP] ← R5
the SP ← the SP-. 4, [the SP] ← R4
from the above sequence of operations micro push instruction, the outcome is not difficult in FIG Raspberry Pi RAM stack 5 stack area 10 area memory cells 0x7efff13c ~ 0x7efff13c displayed.
S input single-step execution command again ldmfd line 10 pop instruction (see FIG. 11).
Raspberry Pi ARM register content value and a RAM region of the stack after the execution ldmfd pop instruction Figure 11 shows
in FIG. 11, again used ir command register will be displayed, using the x / 10x 0x7efff13c raspberry send commands display RAM stack area 0x7efff13c SUMMARY unit 10 starts the word units.
Pop instruction ldmfd {R0-R3, R9} implementation SP !, raspberry allocation by Figure 12.
12 pop instruction ldmfd SP !, {R0-R3, R9} implementation of raspberry send
ldmfd SP !, {R0-R3, R9} sequences of micro-operations corresponding to the pop instruction is as follows:
[the SP] → R0 , the SP +. 4 → the SP
[the SP] → Rl, the SP +. 4 → the SP
[the SP] → R2, the SP +. 4 → the SP
[the SP] → R3, the SP +. 4 → the SP
[the SP] → R9, the SP +. 4 → the SP
from the above sequence of operations micro pop instruction, the outcome is not difficult to FIG. 125 registers R0 ~ R3 and R9 display. Finally, enter q / quit quit GDB debug command state and return to the terminal Raspberry Pi Linux command prompt.
End. Of This Lecture
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Published: 19 March 2020
