Girlfriend to apply for hardware engineers, test her interviewer OC door, OD door and push-pull output!

Pen questions hardware engineers often Examination OD OC doors and gates, some on the interview to ask more OC or OD doors can be composed of multiple lines and structures, more frequent and Structure line, there is a push-pull output there are some microcontroller GPIO made using this structure, as the most common STM32.

Original bloggers: Excellent AirCity , has been reprinted consent.
Original link: OC doors and door OD

1. OC door

OC open collector means, the following structure:

A = 0, ① off, ② ON, corresponds to the switch is closed, the output of 0V (0V actual output is not, because of the transistor saturation voltage).

A = 1, ① turned on, ② off, corresponds to the switch OFF, C high impedance point, C point have pull-up resistors normally, to output a high level.

I2C, SMB bus type door is OC or OD door, but also because such a high impedance output and IO "line and logic" in order to enable them to have a master, multiple slave, not short-circuit conditions.

Caution:

1. Pull-up resistor is too small, the saturation voltage increases, resulting in a high output from a low level.
2. Pull-up resistor is too large, the rising edge of delay signal.
3. OC gate can be tied together, do "lines and logic."
4. Pull-up voltage can be selected according to the standard level at an input terminal, an output port of the chip but also noted that the maximal rating voltage

2. OD door

OC gate into the transistor FET, the gate is OD, OD means open drain.

A = 0, ① off, ② ON, corresponds to the switch is closed, the output of 0V (since the on-resistance of the MOS transistor is low, the output is nearly equal to 0).

A = 1, ① turned on, ② off, corresponds to the switch OFF, C high impedance point, C point have pull-up resistors normally, to output a high level.

I2C, SMB bus type door is OC or OD door, but also because such a high impedance output of IO, and "logical line" in order to enable them to have a master, multiple slave.

Caution:

1. Pull-up resistor is too small causes ② MOS transistor conduction current is too large, burning MOS transistor.
2. Pull-up resistor is too large, the rising edge of delay signal.
3. OD door can be tied together, do "wired-AND logic."
4. Pull-up voltage can be selected according to the standard level at an input terminal, an output port of the chip but also noted that the maximal rating voltage

3. Push-pull output

Push-pull output, also known as push-pull, GPIO many parts of the chip will support this feature.
NPN + PNP fabricated using a push-pull output structure is as follows:

a PMOS + NMOS push-pull output structure fabricated as follows:

$1. When the input output high, PMOS is turned off, NMOS is turned on, output = 0V$
$2. input when the output low, PMOS is turned on, NMOS is turned off, output = VDD$

Push-pull output configuration of the low-level output capability OD OC gate or door is the same, but much stronger than the high output capacity OD OC gate or door, because it is pulled up to the power supply directly! Thus push-pull current output can be very high.

Note that, configured as two pin push-pull output, if serialized together, configured as a high-output, and another configured for low output, it will generate a lot of current, resulting in IO burned.

Ha ha ha, my girlfriend is compiled ~

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Always believe that good is about to happen , the author remembers Cheng, Anhui Hefei, reprinted time 2020-03-15 PM14: 40