Many beginners, STM32 developers using library functions when not know how to modify the system clock speed? I do not know how to modify the external crystal frequency?
Here, we focused on these two issues, to give you a simple tutorial. Hope that we can grasp the future can be easily modified frequency 8M crystal frequency 72M 12M modified to change STM32F1 firmware libraries, defined in the frequency external crystal inside stm32f10x.h follows:
! [Mw_shl_code = C, to true] #if defined HSE_VALUE
#ifdef STM32F10X_CL
! #Define HSE_VALUE ((uint32_t) 25000000 or) / * <The External of the Value * in Hz Oscillator /
#else
#define HSE_VALUE ((uint32_t) 8000000) / *! <The External Oscillator in the Value of Hz * /
#endif / * STM32F10X_CL * /
#endif / * HSE_VALUE * / [/ mw_shl_code]
wherein, HSE_VALUE is the frequency of the external crystal, for general-purpose STM32, the default is 8M, on the Internet, default is 25M.
If we use an external crystal 12M, then the modified values HSE_VALUE: 12000000, can, as follows:
! [Mw_shl_code = C, to true] #if defined HSE_VALUE
#ifdef STM32F10X_CL
#define HSE_VALUE ((uint32_t) 25000000 or) / * <! of External Oscillator in at The Value Hz * /
#else
#define HSE_VALUE ((uint32_t)12000000) /*!< Value of the External oscillator in Hz */
#endif /* STM32F10X_CL */
#endif /* HSE_VALUE */[/mw_shl_code] 
Then, still using the frequency of 72M, in which system_stm32f10x.c, the following macros:
#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (STM32F10X_HD_VL defined)
/ * #define SYSCLK_FREQ_HSE HSE_VALUE * /
#define SYSCLK_FREQ_24MHz 24 million
#else
/ * #define SYSCLK_FREQ_HSE HSE_VALUE * /
/ * #define SYSCLK_FREQ_24MHz 24 million * /
/ * #define SYSCLK_FREQ_36MHz 36 million * /
/ * #define SYSCLK_FREQ_48MHz 48 million * /
/ * #define SYSCLK_FREQ_56MHz 56 million * /
#define SYSCLK_FREQ_72MHz 72 million
#endif
default definition a: SYSCLK_FREQ_72MHz 72000000, i.e. 72M, so do not change here, but, in fact, modify 72M is clocked by
SetSysClockTo72 achieve the function, the function of the core code is as follows:
RCC-> & CFGR = (uint32_t) ~ (RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC-> CFGR | = (uint32_t) (RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL9);
#else
/ * the PLL Configuration: = PLLCLK the HSE. 9 * * = 72 MHz /
RCC-> & CFGR = (uint32_t) ((uint32_t) ~ (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
RCC_CFGR_PLLMULL));
RCC-> CFGR | = (uint32_t) (RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
#endif / * STM32F10X_CL * /
/ * * the Enable the PLL /
RCC-> CR | = RCC_CR_PLLON; wherein the central frequency of the modified code:
RCC-> CFGR | = (uint32_t) (RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
by RCC_CFGR_PLLMULL9 the multiplier factor is set to 9, if the default external crystal is 8M, 72M to obtain the frequency just then.
However, we modify the external crystal for the 12M, so here was changed to 6, the revised code is as follows:
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
8M crystal 
16M and then the crystal frequency divided by 2 = 72 * 9 
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