The reason static power generated

From the 1980s began using CMOS circuits, circuit designers will appreciate the advantages of this technology, but with advanced
technology accompanied by the growing power consumption. In the early circuit design, static power is not the focus of consideration. This is
because at this stage, the power consumption of CMOS circuit largely depends on switching activity of the circuit, when the circuit flipped activity stops
, the static power consumption almost negligible.
With advances in semiconductor technology, the line width is further reduced, this case must also decreases the supply voltage to the gate oxide layer can accommodate
the electric field strength to bear. FIG is a schematic view of a CMOS transistor shown in Figure 1-2. When the process time reaches 90nm, the gate oxide
layer thickness (TOX) has been reduced to. 12A, this time must be reduced to ensure that the gate voltage of the gate oxide layer insulating effect. In order to ensure that each
performance requirements on behalf of the process, reducing the threshold voltage is necessary. 5V power supply voltage threshold at 1.25V Age Age 1V power
obviously no longer applicable.

In the modern semiconductor processes, reducing the threshold voltage becomes an important effect in increasing the power consumption of the CMOS circuit due to leakage
factors. In general, the threshold voltage of 65mV per reduced, along with sub-threshold leakage will increase exponentially. Dynamic power consumption while the circuit will vary with
reduced supply voltage decreases. In the circuit design of the 90nm process technology, the proportion occupied by the static power continues to increase.
Focus on power control will not only reduce dynamic power consumption, but also must consider reducing static power consumption.