LLVM Notes (7) - side effect instruction

What is the side effect of the command
is often seen MI.hasUnmodeledSideEffects () at the rear end optimization this interface, which represents the instruction has not measurable side effects. For such instructions, the compiler optimization process will be conserved, such as instruction scheduling will be this boundary (instruction scheduling after it has not before).
See the instruction side effect attribute
instruction different architectures usually defined in [llvm_build_dir] / lib / Target / [arch] / [arch] GenInstrInfo.inc file (directory where llvm_build_dir for building, arch of specific architectures). Listed below several (at ARM architecture) comprising a common side effect instruction: stack reduction (directives), CAS 32 (directive), jump, exclusive access, the access status registers visible to the compiler for all of the constraints can not be understood. (stack growth / reduce function must start / end, atomic, exclusive access) have been described as a side effect, and the load / store instruction does not like the tag with.

  { 179,    4,  0,  0,  1028,   0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo42, -1 ,nullptr },  // Inst #179 = ADJCALLSTACKDOWN
  { 195,    5,  2,  0,  1029,   0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #195 = CMP_SWAP_32
  { 626,    1,  0,  4,  855,    0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #626 = BLXi
  { 635,    0,  0,  4,  841,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #635 = CLREX
  { 746,    8,  0,  4,  847,    0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo164, -1 ,&getMCRDeprecationInfo },  // Inst #746 = MCR
  { 1793,   7,  1,  4,  946,    0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr },  // Inst #1793 = STRB_POST_REG

The side effect attribute setting instruction
default base instruction (instruction indicates no pattern matching) the default properties comprising side effect. This is because the basis for the definition of hasSideEffects Instruction is?, Which is the default (see include / llvm with the side effect / Target / Target.td). If the instructions need not be explicitly specified attribute this property is zero (or vice versa), the ARM instruction, for example, stack growth / reduction command need to explicitly specify the side effect, while constant without specifying side effect:

let hasSideEffects = 0, isNotDuplicable = 1, hasNoSchedulingInfo = 1 in
def CONSTPOOL_ENTRY :
PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
                    i32imm:$size), NoItinerary, []>;
let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
def ADJCALLSTACKUP :
PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
           [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;

def ADJCALLSTACKDOWN :
PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary,
           [(ARMcallseq_start timm:$amt, timm:$amt2)]>;
}

When hasSideEffects attribute is not specified the default table-gen process comprising conserved side effect properties, but sometimes does not onset default attributes. This is due to the side effect pattern matching property default coverage instruction side effect properties. In ARM store instruction example:

multiclass AI2_stridx<bit isByte, string opc,
                      InstrItinClass iii, InstrItinClass iir> {
  ...
  def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
                (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
                IndexModePost, StFrm, iir,
                opc, "\t$Rt, $addr, $offset",
                "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
    // {12}     isAdd
    // {11-0}   imm12/Rm
    bits<14> offset;
    bits<4> addr;
    let Inst{25} = 1;
    let Inst{23} = offset{12};
    let Inst{19-16} = addr;
    let Inst{11-0} = offset{11-0};
    let Inst{4} = 0;

    let DecoderMethod = "DecodeAddrMode2IdxInstruction";
  }
  ...
}

defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
                         am2offset_reg:$offset),
             (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
                           am2offset_reg:$offset)>;

store instruction does not specify hasSideEffects, inc reasonably generated file will contain the property, but it has been shown above, the instruction does not exist side effect. This is because the pattern post_store corresponding node is ISD :: STORE, the node has no side Effect.
regard to the specific implementation of instr property setting pattern can be found in the code table-gen. CodeGenDAGPattern :: InferInstructionFlags defined in utils / TableGen / CodeGenDAGPatterns.cpp in (), the interface will be set according to the corresponding instruction pattern side effect properties detecting whether the instruction corresponding to the side effect of all attributes consistent pattern.

static bool InferFromPattern(CodeGenInstruction &InstInfo,
                             const InstAnalyzer &PatInfo,
                             Record *PatDef) {
  ...
  if (InstInfo.hasSideEffects != PatInfo.hasSideEffects &&
      !InstInfo.hasSideEffects_Unset) {
    if (!InstInfo.hasSideEffects) {
      Error = true;
      PrintError(PatDef->getLoc(), "Pattern doesn't match hasSideEffects = " +
                 Twine(InstInfo.hasSideEffects));
    }
  }
  ...
  InstInfo.hasSideEffects |= PatInfo.hasSideEffects;
}
void CodeGenDAGPatterns::InferInstructionFlags() {
  ...
  for (const PatternToMatch &PTM : ptms()) {
    ...
    Errors += InferFromPattern(InstInfo, PatInfo, PTM.getSrcRecord());
  }
  if (Target.guessInstructionProperties()) {
    ...
    if (InstInfo->hasSideEffects_Unset)
      InstInfo->hasSideEffects = true;
  }
}

About side effect summary:

You can explicitly declare the attribute definition instruction defined pattern.
table-gen priority when automatically generating the pattern of side effect attributes to the copy instruction.
Instruction will be used only when an instruction pattern is not present side effect properties.
If no instructions exist pattern is not explicitly declared it will default to the side effect properties.
Pattern corresponding to the instruction is present in the side effect is explicitly declared valid (even if the corresponding pattern without side effect), but the statement with a pattern corresponding to the side effect without side effect being given instructions.

LLVM Notes (7) - side effect instruction

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