First, the FET works
FET (Field Effect Transistor Acronym (the FET)) referred to FET . There are two main types: JFET (junction FET-JFET) and a metal - oxide-semiconductor field effect transistors (metal-oxide semiconductor FET, referred to as MOS-FET). Participation by most conductive carrier, also known as unipolar transistors. It belongs to the voltage-controlled semiconductor device. Having a high input resistance (10 ^ . 7 ~ 10 ^ 15 [Omega]), small noise, low power, high dynamic range, ease of integration, there is no phenomenon of second breakdown, the advantages of wide safe operating area, and has become a bipolar transistor power transistor powerful competitors.
Second, the classification FET
Press different channel semiconductor material, and an insulated gate junction type N-channel and P sub-channel two kinds.
The field effect transistor can be divided into field effect transistor and a MOS field effect transistor. The MOS field effect transistor is divided into N channel depletion type and enhancement type; and P-type depletion enhancement grooves four categories. See below.
Third, the field-effect transistor type designation
There are two existing naming method:
A first bipolar transistor and method of naming the same, the letter J on behalf of the third junction field effect transistor, an insulated gate field effect transistor on behalf of O, the second letter represents material, D is a P-type silicon, N is the inversion layer channel; C is a P-channel N-type silicon. For example, 3DJ6D a junction type N-channel field-effect transistors, 3DO6C N-channel insulated gate field effect transistor.
The second method is named CS ×× #, CS represents the FET, ×× to figures represent the number of models, # with letters on behalf of the same model in different specifications. For example CS14A, CS45G like.
Fourth, the parameters of the FET
FET many parameters, including the DC parameters, communication parameters and limit parameters, but generally when using following main parameters:
. 1, the I the DSS - saturated drain-source current. It refers to a junction type or a depletion type insulated gate field effect transistor, the gate voltage of the U- GS = 0, the drain-source current.
2, the U- P - pinch-off voltage. It refers to a junction type or a depletion type insulated gate field effect transistor, the gate-drain voltage when the source is turned off immediately.
3, U T - turn-on voltage. It refers to an insulated gate enhancement mode field effect tube, so the gate-drain voltage when the source is turned on immediately.
. 4, G M - transconductance. Is a gate-source voltage of the U- GS - drain current of the I D control capability, i.e., the drain current of the I D variation of the gate-source voltage of the U- GS ratio of the amount of change. G M is an important parameter to measure the ability of amplification FET.
. 5, the BU the DS - drain-source breakdown voltage. It refers to a gate-source voltage the U- GS is constant, the maximum drain-source voltage of the FET can withstand normal operation. This is an extreme argument, applied to the FET operating voltage must be less than BU DS .
6, P the DSM - the maximum power dissipation. Limit is a parameter, is the maximum power dissipation when the drain-source FET performance is not deteriorated allowed. In use, the actual power FET should be less than P the DSM and leave some margin.
. 7, the I the DSM - the maximum drain-source current. Limit is a parameter, means that when the FET is working properly, the maximum current through the drain-source allowed. FET operating current should not exceed the I the DSM
The main parameters of several commonly used field-effect transistor
Fifth, the role of FET
1, may be applied to amplifying FET. Because of the high input impedance FET amplifier, the coupling capacitance can be smaller capacity, without the use of an electrolytic capacitor.
2, high input impedance FET is suitable for impedance transformation. Commonly used in the input stage of the multi-stage amplifier for impedance conversion.
3, variable resistance FET may be used.
4, FET can be conveniently used as a constant current source.
5, FET can be used as an electronic switch.
Test six FET
1, identifies the pin junction field effect transistor
the gate of the FET corresponds to the base of the transistor, the source and drain correspond to the emitter and collector of the transistor. The multimeter R × 1k file, table T with two measuring positive and negative resistance between each of the two pins, respectively. When positive, a negative resistance equal between two pins are several KΩ, then the two pins to the drain D and the source S (interchangeable), the remaining one pin is the gate G . For four pin junction type field effect transistor, a further electrode is shielded pole (ground in use).
2, it is determined gate
electrode touch the tube with a multimeter black pen, respectively, the red pen to touch the other two electrodes. If the two measured resistance is very small, forward resistance are described, belonging to the N-channel FET tube, the black pen is the gate contact.
Manufacturing process determines the source and drain of the FET is symmetrical and can be used interchangeably, does not affect the normal operation of the circuit, it is not necessary to distinguish. Resistance between the source and the drain is about several kilo-ohms.
Note that this method can not be determined a gate insulating gate type field effect transistor. Since such a tube is extremely high input resistance, a small inter-electrode capacitance between gate and source, as long as the measured amount of electric charge, high voltage can be formed in the inter-electrode capacitance, the tube is easily damaged.
3, amplification capability estimate FET
multimeter appropriated R × 100 stalls, the red pen then the source S, a drain D connected to the black pen, FET is equivalent to the power supply voltage of 1.5V plus. At this time indicating hands are inter electrode resistance value DS. Between fingers and gate G, the induced voltage of the body as an input signal applied to the gate. Since the amplification of the tube, the UDS and ID will change, also corresponds to the resistance change between electrodes DS, the hands can be observed relatively large swing. If pinching hands swing gate is very small, indicating weak amplification capability of the tube; if the hands do not move, that the tube has been damaged.
Operating point due to the higher 50Hz alternating voltage induced in the human body, different profile measurements of the field effect tube resistance may differ, so when the hands may Yong Shounie right swing gate, it may swing to the left. Few tubes RDS decreases, so hands swinging to the right, most of the tube RDS increases, the swing left hands. Regardless of the direction of swing of the hands, as long as there is obviously swing, it means that the tube has an enlarged capacity.
This method is also applicable to the measured MOS transistor. To protect the MOS FET must be insulated hand holding screwdriver handle, with a touch gate metal rod to prevent the human body sensor is directly applied to the gate charge, damage to the tube.
MOS transistors each measurement is completed, a small amount of charge will be charged with GS junction capacitance establishing voltage UGS, and then followed by the timekeeping hands may not move, when the inter-electrode short circuit GS click.
Currently pin order of the conventional junction type field effect transistor and a MOS-type insulated gate field effect transistor as shown below:
Seven common utility duct field
1, MOS FET
i.e. metal - oxide - semiconductor field effect transistor, the abbreviation of MOSFET (Metal-Oxide-Semiconductor Field -Effect-Transistor), an insulated gate type belongs. Its main feature is a layer of silicon dioxide insulating layer between the metal gate and the channel, thus having a very high input resistance (up to 1015Ω). It also points the N-channel and P-channel tube pipe, the symbol as shown in FIG. The substrate is usually (the substrate) and the source S connected together. According to the different ways of conducting, MOSFET is divided into enhanced, depletion type. The so-called enhanced means: When VGS = 0 is the form of the tube when the OFF state, with the right rear VGS, the majority carriers are attracted to the gate, so "enhanced" of carriers in the region, a conductive channel is formed . It refers to the depletion type, i.e. when VGS = 0 channel is formed, with the right when VGS, majority carriers can flow out channel, and thus "depleted" of the carrier, the tube turned off.
N-channel example, it is made of two highly doped source diffusion region on the P-type silicon substrate with N + and N + drain diffusion regions, and then led out of the source S and the drain D. The source and the substrate inside the communication, both the total retention potential. Top direction in FIG. 1 (a) is a symbol from outside to inside, showing the P-type material (substrate) means an N-channel body. When the bobble positive power supply, and a source connected to the negative power supply VGS = 0, the channel current (i.e., current drain) ID = 0. Gradually increased as the VGS, attracted by the positive voltage of the gate, between the two diffusion regions is induced minority carriers are negatively charged, the N-type channel from drain to source, VGS is greater than when the pipe when the turn-on voltage VTN (typically about + 2V), N-channel tube starts conducting, a drain current ID.
N-channel MOSFET is typically made products 3DO1,3DO2,3DO4 (all of which are single grid tubes), 4DO1 (double gate tube). They pin arrangement (bottom view) Figure 2.
MOS FET more "fragile." This is because its input resistance is high, and the gate - source capacitance and very small, vulnerable to external electromagnetic or electrostatic induction charging, and the small amount of charge can be formed at a relatively high voltage between the capacitor electrode (U = Q / C), the tube damage. Thus each of the pins when the plants are twisted together and housed in a metal foil, or the G and S poles form equipotential electrode, to prevent the accumulation of static charge. When the tube without all the leads should be shorted. Extreme care should be measured, and take the appropriate sense of anti-static measures.
1.1, a method for detecting MOS field effect transistor
(1), the preparatory work
prior to the measurement, the first body is shorted to ground, in order to touch the contact pins of the MOSFET. Preferably on the wrist and the earth wire connected to a communication, the potential of the holding body and the earth and the like. Then pin separately, then removed wires.
(2), the electrode determines
the multimeter dial to R × 100 stalls, first determine the gate. If a foot and other foot resistance is infinity, showing that the foot is the gate G. Exchange leads weight measurement, the resistance value between the SD should be a few hundred Ohms to several kilo-ohms, which smaller resistance that time, the black pen pole contact is D, the red pen then the S pole. Japanese production 3SK products, S pole and the envelope is turned on, whereby it is easy to determine the S pole.
(3), the ability to check the amplification (transconductance)
The floating electrode G, the black pen then D pole, the red pen then the S pole, and then touched with a finger electrode G, the hands should be greater deflection. Dual-gate MOS field effect transistor having two gates G1, G2. To distinguish, the hand can touch each G1, G2 electrode, wherein the electrode G2 hands is larger deflection amplitude to the left.
Currently, some of the MOSFET increases in GS protection diode between the poles, usually there is no need to short-circuit of the pin.
1.2, MOS field effect transistors precautions .
MOS field effect transistor in the classification should pay attention and can not be interchanged. MOS field effect transistor of high input impedance (MOS integrated circuit comprising a) an electrostatic discharge easily, should pay attention to the following rules:
(. 1), MOS devices are generally mounted on a black conductive foam bag factory, not to self simply take a plastic bag. It may also be connected to the respective thin copper pins together, foil packets, or
(2), remove the MOS device not slip plastic plate, a metal plate applied to stand-contained device.
(3), by electrical soldering iron should be grounded.
(4), before welding should board power supply line and the ground short, then MOS device after completion of welding at separate.
(5), MOS device pin welding order of drain, source, gate. When the reverse order to disassemble.
(6), a circuit board installed prior to, use of a ground wire at each of the clamp touch the terminals of the machine, and then the circuit board Jieshangqu.
(7), the gate of the MOS field-effect transistor under permissive conditions, the best access protection diode. Note that the access circuit should check whether the existing protection diode damage.
2, VMOS FET
VMOS FET (VMOSFET) referred to the pipe or VMOS power FET, which is called the V-groove MOS FET. It is the second MOSFET newly developed high-efficiency, power switching devices. It not only inherited the high input impedance MOS FET (≥108W), the drive current is small (approximately about 0.1μA), further having a high voltage (maximum voltage 1200V), a large operating current (1.5A ~ 100A), an output high power (1 ~ 250W), good transconductance linearity, fast switching speed and other excellent properties. Because of the advantages of the power transistor will rolled into tubes, and therefore widely used in the voltage amplifier (voltage amplification factor up to several thousand times), the power amplifier, and an inverter switching power CKS.
It is well known, the conventional MOS FET gate, a source and drain is substantially the same maximum level of the chip, the operating current flows substantially in a horizontal direction. VMOS tube is different, it can be seen from the lower left its two structural features: a first, V-shaped grooves metal gate structure; second, a vertical conductivity. Since the drain is led out from the back of the chip, the chip ID is not in horizontal flow, but the weight of N + doped regions (source S) starting flows through the P-channel lightly doped N- drift region, finally down to the vertical drain D. As indicated by the direction of the current, because the flow cross sectional area increases, so that by a large current. Since the chip between the gate and the silicon dioxide insulating layer, so it is still MOS insulated gate field effect transistor.
The main manufacturers of domestic production of VMOS FET 877 Plant, Tianjin semiconductor device four plants, Hangzhou tube factory, typical products VN401, VN672, VMPT2 like. Table 1 lists the main parameters of six kinds VMOS tube. Wherein, IRFPC50 appearance as shown in the upper right in FIG.
Detection method 2.1, VMOS FET
(1), the gate G is determined that
the multimeter dial to R × 1k profiles were measured resistance between the three pins. If it is found a word to its foot legs showed infinite resistance, and after an exchange of lead is still infinity, then prove that this pin is G electrode, and the other two pins as it is insulative.
(2) determines the source S, the drain D
seen from Figure 1, the source - has a PN junction between the drain, and therefore based on the PN junction is forward, reverse resistance differences, and D can identify the S-pole electrode. Two switching table using the measured strokes resistance, wherein the resistance value is low (typically a few thousand to ten thousand European ohm) resistance of a forward, then the black pen is the S pole, the red pen then D electrode.
(3), measuring the drain - source on-state resistance RDS (on)
will be shorted GS, selecting multimeter R × 1 file, the black pen then the S pole, the red pen then D electrode, the resistance should be a few in Europe to ten and Europe .
Because different test conditions, measured RDS (on) than the typical values given in the manual to be higher. For example 500 multimeter R × 1 type VMOS speed Found IRFPC50 a tube, RDS (on) = 3.2W, greater than 0.58W (typical value).
(4). Check transconductance
The multimeter R × 1k (or R × 100) file, then the S pole red pen, the black pen then D electrode, a gate handheld screwdriver to touch, the hands should be clearly deflection, the greater the deflection, tube transconductance higher.
2.2 Notes
(1), VMOS tube also points P-channel N-channel tube and the pipe, but the vast majority of products are N-channel tube. For P-channel tube, the measurement should lead to the exchange position.
(2), a small tube between VMOS GS have protection diodes, the present detection method is no longer applicable items 1.
(3), on the market there is a VMOS tube power module, designed for AC motor speed controller, using an inverter. IR e.g. U.S. produced IRFT001 modules, internal N-channel, P-channel in each of the three, constituting a three-phase bridge configuration.
(4), now commercially available VNF series (N-channel) products, produced in the United States Supertex UHF power FET, the maximum operating frequency fp = 120MHz, IDSM = 1A, PDM = 30W, small signal common source low-frequency transconductance gm = 2000μS. For high-speed switching circuits and radio communication devices.
(5), must be added when using VMOS tube after suitable heat sink. In the VNF306 for example, the installation of the radiator tube 140 × 140 × 4 (mm), the maximum power in order to achieve 30W
VII Comparison of the transistor FET
(1), the FET is a voltage control element, the transistor is a current controlling element. In the case where only takes less current from the signal source, the FET should be used; and the voltage signal is low, and under conditions allowing to take more current from the signal source, the transistor should be used.
(2), field-effect transistor using a conductive majority carriers, so called unipolar device, that is while the transistor is a majority carrier, and the use of minority carrier conduction. It is called bipolar.
(3), some of the source and drain of FET may be used interchangeably, the gate voltage may be positive or negative, good flexibility than transistors.
(4), the FET can operate at very low current and voltage, and its manufacturing process can easily put a lot of FET integrated on a silicon chip, and therefore large scale integration FET the circuit has been widely used.
To explain the working principle of the MOS FET, we first look at the work process contains only a P-N junction diode. As shown below, we know that the diode forward voltage is applied (P positive termination, N cathode termination), the diode is turned on, the current through the PN junction. This is because the P-type semiconductor is a positive voltage terminal and negative electrons in the N-type semiconductor are attracted to the P type semiconductor flock plus terminal of the positive voltage, electrons in the n-type semiconductor P toward the terminal end of the N-type semiconductor motion, thereby forming a current conduction. Similarly, when the diode is reverse voltage (negative termination P, N termination positive), then the P-type semiconductor side is negative voltage, positive electrons are gathered at the end of the P-type semiconductor, the negative electrons are accumulated in the N end-type semiconductor, electrons do not move, no current flows through PN junction, the diode is turned off.
For FET, when the gate voltage is no, the foregoing analysis shows that, between the source and the drain current does not flow through, this time with the off-state FET. When a positive voltage is applied to the gate of N channel MOS FET, since the electric field, at this time a negative electron source and the drain of the N-type semiconductor are attracted out of the flock to the gate, but the barrier oxide film, so that electrons accumulated in the P-type semiconductor between the two N-channel, thereby forming a current, so that conduction between the source and the drain. We can also think of as a trench, a gate voltage is established between the two N-type semiconductor corresponds to take a bridge between them, the size of the bridge size determined by the gate voltage.
The following figure shows the processes and P-channel MOS FET, which works with the same N-channel MOS FET is not repeated here.
The following briefly enhanced during operation of the MOS FET circuit applications thereof. A circuit enhancement P-channel MOS FET and an enhancement type N-channel MOS FET in combination.
When the input terminal is low, P-channel MOS FET is turned on, the positive output terminal of the power supply is turned on. When the input is high, N-channel MOS FET is turned on, the output terminal of the power source turned on.
In this circuit, P-channel MOS FET and N channel MOS FET is always operated in the opposite state, opposite to the phase input terminal and an output terminal. In this work we can get a larger current output. At the same time due to leakage current, so that in the absence of gate voltage to 0V, typically less than 1 to 2V, MOS FET is turned off only when the gate voltage. Different FET turn-off voltage which is slightly different. Precisely because of this, so that the two circuits will not be turned on simultaneously short the power supply.