A, CPU multi-level cache - to optimize order execution
Processor or compiler to improve processing speed has been made to optimize the code violation of the original sequence.
Reordering follow the principle of as-if-serial
as-if-serial semantics: no matter how reordering (compiler and processor in order to improve the degree of parallelism), the execution result (single-threaded) does not change the program.
Compiler, runtime and processors must comply with as-if-serial semantics.
In order to comply with as-if-serial semantics, the compiler and the processor does not make the operation of reordering data dependencies, since such reordering can change the result.
However, the absence of data dependencies between operations if these operations could be reordered compilers and processors.
E.g:
a=10; b=200; result=a*b;
Its dependency as shown below:
Since a = 10 and b = no dependency exists between 200, the compiler or the processor may rearrange these two operations, so the final order of execution may have the following two situations:
But no matter what the order of execution, the end result is right.
It is because of the presence of as-if-serial, we are in the preparation of single-threaded programs will feel as if it is in the order of execution of the code, which we can not be concerned about the impact rearrangement.