Godson hardware and software training personal summary -day1

The first day focused on the hardware design, push them to the end of production of 3A4000 + 7A1000. Here I can only record a few of their own interest.

1,3A4000 / 3B4000 processor

    Support 256 vector instruction; processor optimized package, no further compatible Godson 3A1000,3A3000 / 3B3000, size reduced to 37.5mm x 37.5mm, the number of pins increased to 1211. In addition to interface definitions up PCI interface, the LPC interface of memory upgrade DDR3 / 4 interface; a plurality of processors interconnected sheets were substantially optimized, cross-piece access memory bandwidth increase exponentially, enhanced multiplex system expansion; enhanced floating point operation; improvement compared to 3A3000 / 3B3000 of:

                Clock speed;

           HT controller architecture for low latency, high bandwidth optimization;

          Support processor core dynamic FM regulator; (the problem did not give a more detailed explanation, smart regulation is to rely on software design users)

          An increase of 8 interconnection support; (compare to the effort)

 

2, the hardware design may need to pay attention

            a, 3A4000 added BBG, within the integrated bias generation module.

            Increase in forward bias in favor of lifting frequency, but increases power consumption; increase the reverse bias voltage helps reduce power consumption.

            Server, desktop and other low-power design is insensitive to recommend positively skewed connections, laptops and other low-power sensitive designs recommendation reverse bias connection, here Godson hardware engineers say they have proven anti-bias, and is now being positively skewed verification.

            b, SE floating pin when not in use. (This feature is currently not open to users)

           c, regardless PCIE controller using an internal clock or an external clock, and peripheral controller PCIE clock homology requirements. When an external clock PCIE controller, the controller uses the input port of the clock needs access. (Homologous question did not give a detailed explanation, but requires attention must be homologous)

            d, RTC power control to be in the range of 2.5 ~ 2.9V, the chip is now written manual is 3V, subsequent modify. (Note that this, if the RTC voltage is not in the high temperature range will be cold, too fast too slow clock and other anomalies)

            e, 3A4000 IIC bus to note IIC0 fixed configuration for the master, IIC1 fixed configuration as slave, and try not to change the basic use of Godson given to strictly abide by their hardware design specifications.

            F, show only a DVO, require the user to design converter circuit HDMI, VGA and other interfaces may be provided official selection and technical support as the conversion chip.

            h, debug serial port UART0, try not to change the debug serial port configuration. (Explanation is needed to modify the firmware, firmware changes required to support Godson, too much trouble, no proposed changes)

   In short, it is to be familiar with the hardware design specifications Godson, his strict adherence to design specifications.

 

3, Godson UEFI Introduction

        About this explain the basic read read ppt. UEFI understanding of, and introduce some bias I understand, probably have their own views. Engineers generally introduced under UEFI architecture, programming, code structure, compiling and programming on the Godson, explanation is given of the feature is currently not available to the user operation, there is no point of particular concern. (Man came and lifted temporarily not open to you, a little boring)

 

4, on the PMON

      Major topics of the source structure and some basic configuration, the compiler programming. Did not mention any particular attention, is the basic document to pressing operation, mainly for bridge chip program 7A1000, in fact, is the hardware specifications for the bridge piece more.

 

Basically these, mainly on combat against some simple serial port, display, iic device configuration file tree to explain, can debug, memory debugging, in fact, is a general introduction firmware specification.

    Need relevant information of public concern can be the first number, two days after finishing uploaded to the server to download.

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Origin www.cnblogs.com/shanchen/p/11741765.html