In the computer, typically an arithmetic addition or subtraction is always done with complement. Rule is that:
[the Y X-+] Complement = [X] Complement + [Y] up, [XY] Complement = [X] Complement - [Y] Complement = [X] Complement + [-Y] Complement
This indicates that, with complement representation is plus (minus) addend (minus) number, to complete the calculation of the difference represented by the two's complement sum of the number or numbers of the two, with only the implementation of two's complement numbers applied directly to subtraction, the sign bit and magnitude bits equal treatment, together participate in operations, if the operation result does not overflow, i.e., without departing from the scope of computer that can be represented by the magnitude bits and a sign bit of the result at the same time to the correct value. In addition, it can also be seen when implementing subtraction by the adder circuit is still, the negative complement subtrahend sent to the adder. After the number has a complement, the complement of a negative number this number is simply the bitwise complement of the number of re-inverted to obtain the lowest bit plus one. For example, [the Y] = 101101 complement is [-Y] = 010011 complement, which greatly simplifies the algorithm and the addition and subtraction of lines used for addition and subtraction.
The following question is how to check the overflow of addition and subtraction. There are typically three of expression (say):
(1) two's complement number the same reference numerals are added, and if the sign of addend opposite sign, or a sign opposite two's complement subtraction number, the sign of the difference subtrahend the same reference numerals, and belong to an overflow. This determination method with different complicated to add or subtract the difference between two different operational cases, also the inspection result of the symbols wherein the symbol operand, it is rarely used;
(2) when the number of phases of two's complement subtraction, if the maximum value of the transmitted symbol bits bit carry value sign bit is sent to the higher bit of the values are not identical, but also an overflow.
(3) In the dual-bit symbol (such as fixed point decimal complement modulo 4) calculation, if the two bits have different values a symbol (01 or 10) is an overflow. 01 indicates two positive numbers together, the result is greater than the maximum positive number that can be represented by a machine, called "overflow"; 10 show two negative and the result is less than the machine can be represented by the minimum negative number, referred to as "underflow "; double sign bit of the sign bit high, regardless of whether the results overflow, are the result of the operation right of the sign bit, this conclusion is very meaningful in the multiplication process. Note that in the embodiment dual sign bit, when the internal registers and memory for storing data, a symbol only memory, double the symbol bit adder circuit only in part.
Again, three different versions are slight differences with a statement of fact, the line can be used when implementing differ, but the essence of the problem is exactly the same. See [X] Complement + [Y] where complement arithmetic:
01011 10101 10100
+ 01000 + 11000 + 11001
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10011 101101 101101
（1） （2） （3）
10111 001011 110111
+ 10101 + 001000 + 110101
101000 010011 1101100
（4） （5） （6）
These are all overflow condition, prior to use a sign bit 4, two symbol using the two bits. Here explained by any of the statements in front of that overflow are possible. For example, (1), from the positive plus positive too negative, or data bits transmitted to the sign-bit carry value is 1, the sign bit is sent to the higher bit of the value it is 0, the two are not the same, or ( 5) using a double symbol bit program, which is double the sign bit 01, is an overflow.
Where the complement subtraction result is not the case, are not overflow, sign bit and bit values results are correct. Although the adder are discussed herein, also apply to the subtraction. N n plus n equal burdens, Save n n n equivalents plus negative, as stated earlier, subtraction is done by the adder. For example:
0,101,111,101,001,011 111101
+ 00100 + 11010 + 000100 + 111010
0,111,110,111,001,111 110111
(1) (2) (3) (4)
(1), (2) using a sign bit, (3), (4) using two symbol bits, the sign bit is sent to a higher bit of the value, whether a value of 0 or 1 shall be discarded after modulo .
With the above description, it is possible to complete the addition and subtraction using two's complement code logic 2.5 of FIG.
Before the operation, X, Y registers store the plus (minus) addend (minus) number, the calculation result stored back in register X; F. Adder, capable of receiving two X → F under the control and command signals Y → F data register is complete and adding the operation result under control of the command signal F → X X register received back.
To achieve subtraction, should a negative Y-register code data to the adder complement represents F, which can be sent by the inverted Y-register for each data bit a given input signal into the work done in the lowest position F, with / Y → F 1 → F and a control command is implemented.