x86 boot sequence
CS + EIP decided to start address.
CS and the rear portion 4 0, left shift of 4 equivalent. After the short is to make CS left four plus EIP to get the address to jump.
Content 0x7c00 place to start is the 512-byte bootloader. The reason for this is that BIOS can only load one sector, so the system can only be loaded via bootloader.
Section mechanism
Here uCore mechanism does not implement paragraph, because it can be easily achieved through mechanisms page.
But still not open around the block mode, as long as the start of the period to enable the protected mode (and page-based mechanism to achieve segment base), so we should establish a good mechanism segment. This mapping relationship below approximately equivalent:
Offset figure above is EIP, Seg Selector can be CS can also be other segment registers. Descriptor table descriptor is used to find, index the contents of a segment register, the final descriptor is equivalent to a starting address. Figure above is equivalent linear address to a physical address (start page because no mechanism). If the base is set to 0, then the EIP is the corresponding physical base address.
Descriptor table is the equivalent of an array, the array generated by the operating system, which we call the GDT, global descriptor table. GDT established by the Bootloader. Inside the CPU GDTR This register is used to save GDT. uCore are set to zero in the base address, length are set to 4G.
This tag indicates the figure above segment registers when the current execution of the program in which the privilege level (level 0 represents the system, the larger the number is not more privileged). TI is generally set to 0, ignored, because there is no use the LDT (local descriptor table).
Finally To enable protected mode and eventually into protected mode. Do so much, GDT is to ensure that the mechanism section can still work normally after entering protected mode.
After solving you can begin loading uCore OS.
C function calls
After uCore gain control of the need to understand the relationship between function calls (use an example: When a program error can locate went wrong).
The following is an example to illustrate implementation of C function calls.
Note that the high and low position of the stack, and the order of the push and pop.
This figure is part during a call, to protect the contents of the registers push, push and return address, and then jump to the address of the called function returns after the call completion and then pop the recovery site.
Note that the figure above the return address on the stack.
I began to call the function, note the red box part:
In fact, this is the steps:
The figure is push %ebpthe result of the upcoming EBP points to the address of the stack, shift points to the location has a stack of content on ESP.
Then movl %esp, %ebpto make EBP points to the location pointed to by ESP (ESP and EBP at this time point to the same location). Thus forming a so-called call stack chain. So that you can call to deeper relations to express.
During this period you can see also pushed some call the function they are needed parameters (arguments passed).
Finally face popl %ebp, let EBP redirected to a previously saved address, so they changed back to this:
The last to do retwhen according to ESP will mean return addressto jump.
Therefore, from the above it will be later call foostarts executing the code below.
Finally, run three poplto the very beginning of the press-in parameters to spring back and restore the site.
GCC inline assembly
Inline assembly action: that C language and assembly language may be used mixed.
Examples inserted inside the assembly code in C:
Probably the format:
Clobber the above figure can be temporarily ignored. The three parts are when you want to add constraints, such as limited only to write up a register of the three parts are optional, ie can not write.
one example:
The above example is used to position a first cr0 1, the contents of the first register is read to cr0 %0register inside, and finally the contents of registers are assigned cr0 cr0 memory variable (note the distinction cr0, is a register, a is a memory variable. Also note that the right =rand below :"r"). Then cr0 variable operation (or the operation such that a first position 1). The final step is to write the contents of the variable cr0 back cr0 register (cr0 first variable to a register, then the value of the register to cr0 to register). It is generated corresponding to the following assembly code.
Here are some key words to explain:
another example:
Is the lower right corner corresponding to the keyword register. This code is equivalent to a certain register, the function then calls 0x80, ultimately assigned to __res.
x86 interrupt processing
Examples of soft interrupt: previously mentioned int 80, the software is that you can call the system by soft interrupt to provide services.
Each of the IDT called interrupt gate or trap gate (and prior to the global descriptor table Similarly, also the array), select the trap door to the IDT by the interrupt number, through this trap door / gate may be obtained Interrupt trap door / interrupt gate associated selectors (selectors mechanism similar segment and the segment offset class) section, the last address of the terminal can get the service routine. IDTR table start address in the inside, the start address specified by the operating system.
The picture shows the trap door / gate interrupt information, you can see each item contains a segment selector and an offset. Starting address can be determined by routine these two things.
The figure shows how to determine the exact address of the interrupt service routine by the IDT and GDT / LDT, the interrupt vector is first come into trapdoor select the appropriate index in the IDT / interrupt gate, and the extracted corresponding offset segment select promoter, and finally by the segment selector to select the segment descriptor in the GDT, and finally inside the base address of the segment descriptor extraction (base address). Finally, the last base address and offset combination arrive at a final address of the interrupt routine (interrupt routine is the operating system to be implemented). CPU will automatically be processed according to two tables, so the operating system only need to build two tables and routines on the line. These are the interrupt handling process initialization.
Will interrupt the current program execution after an interruption occurred and jump to execute the interrupt routine (if enabled interrupt at this time, then), after an interruption of the program will return to continue with the currently executing program executed. So here it is related to the process of saving and restoring the site scene. It is to be noted that in different privilege level may correspond to a different approach, descriptor privilege level at which, for example, two low CS, 0 is the kernel mode, user mode is 3. The terminal user mode kernel mode may jump. Privilege level change and no change correspond to different approaches:
First, there is no change in the situation:
Before and after the interrupt is using the same stack.
Oil user mode when switching to kernel mode changes:
Note that the ESP and SS red box, which is used to indicate the stack address in user mode, i.e., before and after the interruption is not to use the same stack.
After the break, the privilege does not change the way the time, iret will pop CS, EIP to jump back to the place continues to interrupt, but will pop up EFLAGS resume flag. ret only pop EIP, then jump to the next instruction to call instruction execution, retf to pop CS and EIP, for remote jump. When privilege changes will pop up showing the contents within the stack shown.
System calls
summary
Figure above GCC inline assembly is embedded inside the assembly code in C, no special meaning.
There will be later blogged about the experiment, I write to you today.