(Reprint)
(In fact, look at the manual to know why)
Q: multi-cycle path hold time check time, why is the default in a cycle before the setup time check, please talk about your understanding?. Such as: Set_multicycle_path -setup 7 -to [whatever] then hold time should be 7-1 this cycle check, and why?
A：
Multi-cycle path check retention time, multiple cycle if you set up time, the hold time to check the previous default set-up time, such as:
the landlord set:
set_multicycle_path -setup. 7 -to [Whatever]
If a period of 10ns time, at this time the data reaches the trigger should be: [60 + Th, 70- Ts]
As to why the one hand and the like is primetime default, while the other is a single inspection cycle, usually required so that data requirements [Th, 10-Ts] arrival time range. (Th represents the hold time, Ts represents the set-up time)
but at the same time if you set the setup and hold times are multi-cycle path constraints, then the delay range can be larger, such as:
set_multicycle_path -setup 7 -to [CLK]
set_multicycle_path -hold 6 -to [get_pins C_reg / D ]
when then the time of check in retention time Th, instead of 60 + Th, the range at this time and the arrival time becomes large
is: [Th, 70- TS]
is generally set to the latter, so that multi-cycle path optimization range of the circuit becomes large.
Reiterate that: using
set_multicycle_path -setup. 7 -to [CLK]
set_multicycle_path -hold. 6 -to [get_pins C_reg / D]
optimum range of the circuit of the multi-cycle path does so large, but there is potential risk of metastable, so be careful!
The only:
set_multicycle_path -setup 7 -to [CLK]
You must also ensure path_delay large enough, no hold-time violation, DC is almost impossible to do this.
Add register-enabling logic to solve the metastable
First of all:
whether it is a single cycle or multi-cycle, hold checks before a default setup of the clock.
After you write set_multicycle_path -setup 7 -to [clk], dc where pt default set_multicycle_path -hold 0 -to [get_pins C_reg / D], if you do not write set_multicycle_path -hold 6 -to [get_pins C_reg / D]
other Harva He said very detailed.
Second:
As mentioned richardhuang1, plus enabled, data mining in mining cycle of the clock.
set_multicycle_path and hold checks
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Question:
I have a path that is set as multicycle path for the setup check. For some
reason, PrimeTime seems to be treating it as a multicycle path for hold time
checking as well. I'm using:
set_multicycle_path -setup 7 -to [whatever]
Why are the hold time checks multicycle?
Answer:
By default, if you specify 'set_multicycle_path -setup X', PrimeTime and
Design Compiler assume the datapath could change during any clock before
clock edge number X. To deal with this situation, PrimeTime and Design
Compiler implicitly add 'set_multicycle_path -hold 0 -to [whatever]'. This
positions the hold check one clock cycle before the setup check, effectively
constraining the path delay to be between X-1 and X clock cycles, or in
equation form:
X-1 cycles + T_hold < path delay (min)
path delay (max) < X cycles - T_setup
So by default the tools assume you want the path buffered up so that the
minimum change is > X-1 cycles.
This may not be the desired behavior. You can move the hold check back
towards the start of the multicycle period by specifying:
set_multicycle_path -hold X-1 -to [whatever]
In the above example, add
set_multicycle_path -hold 6 -to [whatever]
to the constraints and the hold check should occur on the desired edge. Note
that moving this check back requires the designer to handle possible
metastability. If the endpoint is a multi-bit signal, then you may need
to generate register-enabling logic to avoid clocking data before all of
it is valid.