Written on the front of the words
Our data in operation or when stored, are generally present in binary format. But in many cases, we need to show some result of the operation is displayed on the device, if the direct binary form to display it, we will be very easy to see. Therefore, we need to first convert the binary number to decimal then displayed. Binary to decimal conversion There are many ways. In this section, the dream-wing brothers and we will study together the most popular foreign one kind of conversion method - the gradual shift method. In this way, we not only can achieve data format conversion in the absence of the cycle of poor circumstances, and our resource footprint is quite small.
The basic concept
In BCD (Binary-Coded Decimal) also known as binary-coded decimal or di - decimal code. Using 4 binary numbers to represent a decimal number of 0 to 9 of these 10 digital. This BCD code by using a coding format to store four bits of a decimal digital, so that conversion between binary and decimal is performed fast. Such coding techniques in frequently used in the FPGA, such as keyboard input data matrix required when displayed on a digital, digital matrix keyboard input is a binary number, and to be displayed on the LED is a decimal number, it is necessary to binary digital conversion to BCD, which will often encounter in our future designs.
7.3 .3 principle of gradual shift method
In this design, we used to gradually shift method to achieve the conversion of binary to BCD code, before the design, we first look at the principle of converting a binary number to BCD code - the gradual shift method:
Variable definitions:
B: need to convert binary bits wide
D: bit width converted BCD code (wherein the bit width BCD code calculated as follows: The bit width binary number, its maximum and minimum values determined unsigned number can be expressed as the data width is 8 size range of data is 0 to 255, we take the maximum value of 255, corresponding to each of the four digit BCD code, corresponding to three numerals 3x4 = 12-digit BCD)
N: the bit width binary number to be converted BCD code bit width conversion plus
Gradually shift the rules of law:
- Preparing a N-bit shift register;
- Binary number gradually left;
- After each left shift each bit BCD adjustment bigger four plus three;
- After all the shifting binary numbers, the result obtained.
- Design tasks
The design of our task is to convert an 8-bit binary number to BCD
As follows: bit width of the input binary data is B = 8 bits used to represent unsigned words, the size of the input data range is 0 to 255, we take the maximum value of 255, each of which requires a digital 4-bit BCD code He represents, so the length of the BCD code is D = 3x4 = 12 bits.
to sum up:
- Preparing a N = B + D = 8 + 12 = 20-bit shift register;
- Binary number gradually left;
- After each left shift each bit BCD adjustment bigger four plus three;
- After all the shifting binary numbers, the result obtained.
Now, we listed a table to illustrate the gradual shift method:
| The first few times shift |
BCD[11:8] |
BCD[7:4] |
BCD[3:0] |
Bin[7:0] |
| Start |
|
|
|
10100101 |
| 1 |
|
|
1 |
01001010 |
| 2 |
|
|
10 |
10010100 |
| 3 |
|
|
101 |
00101000 |
| 3 |
|
|
1000 |
00101000 |
| 4 |
|
1 |
0000 |
01010000 |
| 5 |
|
10 |
0000 |
10100000 |
| 6 |
|
100 |
0001 |
01000000 |
| 7 |
|
1000 |
0010 |
10000000 |
| 7 |
|
1011 |
0010 |
10000000 |
| 8 |
1 |
0110 |
0101 |
00000000 |
| BCD |
1 |
6 |
5 |
|
From the above table to know:
Bin = 10100101 = 165；
BCD = 0001_0110_0101 = 1_6_5 = 165；
It can be seen, the progressive displacement method is converted into a binary number BCD code.
Top-level block diagram design
We have mastered the basic concepts above and clear design tasks, you can start designing our circuit, the idea of dream-wing brothers is to first establish a bin_to_bcd top module, the main function of this module is the input binary data expansion , then the expanded data is inputted to the level shift module, the final result of the last shift is to take the 12-bit output high; bcd_modify then create a module, the function of this module is the data inputted shift, and high input data into 3 groups 12 are input to the next layer comparison module compares each comparison ends once shifted and output data; cmp last build a module, the main function of this module the input data is added to adjust the senior three, then output. A block diagram of the design of each module are as follows:
bin_to_bcd top frame design
B CD_ Modify module box frame design:
cmp module 's frame design:
Code to achieve
After a good design of the above block diagram, and then we use the Verilog language, to describe the circuit configuration of the above:
bin_to_bcd top-level architecture of the code is as follows:
| /**************************************************** * Engineer: Dream Brother Wing * QQ : 761664056
* The module function: binary revolution 8421BCD code top-level module *****************************************************/ 01 module bin_to_bcd( Bin 02 , // binary input 03 bcd // BCD code output 04 ); 05 06 the INPUT [ 7 : 0 ] bin ; // binary input 07 Output [ . 11 : 0 ] BCD ; // the BCD code output 08 09 wire [19:0] bcd_reg_0,bcd_reg_1,bcd_reg_2,bcd_reg_3,bcd_reg_4, 10 bcd_reg_5,bcd_reg_6,bcd_reg_7,bcd_reg_8; //8次移位结果输出 11 12 assign bcd_reg_0={12'b000000000000,bin}; //把输入的8位二进制数转换成20位 13 14 //第一次移位 15 bcd_modify b1(.data_in(bcd_reg_0),.data_out(bcd_reg_1)); 16 //第二次移位 17 bcd_modify b2(.data_in(bcd_reg_1),.data_out(bcd_reg_2)); 18 //第三次移位 19 bcd_modify b3(.data_in(bcd_reg_2),.data_out(bcd_reg_3)); 20 //第四次移位 21 bcd_modify b4(.data_in(bcd_reg_3),.data_out(bcd_reg_4)); 22 //第五次移位 23 bcd_modify b5(.data_in(bcd_reg_4),.data_out(bcd_reg_5)); 24 //第六次移位 25 bcd_modify b6(.data_in(bcd_reg_5),.data_out(bcd_reg_6)); 26 //第七次移位 27 bcd_modify b7(.data_in(bcd_reg_6),.data_out(bcd_reg_7)); 28 //第八次移位 29 bcd_modify b8(.data_in(bcd_reg_7),.data_out(bcd_reg_8)); 30 31 assign bcd={bcd_reg_8[19:8]}; //取高12位为输出结果 32 33 endmodule |
第9~10行我们定义了9个位宽是20的寄存器，第一个寄存器bcd_reg_0我们存放的是输入数据扩展之后的数据，也就是在第12行我们把输入的8位二进制数转换成了20位；第15~29行我们把bcd_modify模块例化了8次，前一个例化模块的输出总是当前模块的输入，比如第23行，输入的数据是bcd_reg_4，在进行了一次移位之后，输出的数据是bcd_reg_5，然后bcd_reg5又作为下一个第25行例化模块的输入，依次向下一级一级传递，进行了8次移位之后，第31行直接取第8次移位之后的结果的高12位作为转换后的BCD码输出。
bcd_modify模块的代码如下：
| /**************************************************** * Engineer : 梦翼师兄 * QQ : 761664056 * The module function : 移位模块 *****************************************************/ 01 module bcd_modify( 02 data_in, //需要移位比较数据输入 03 data_out //移位比较完成数据输出 04 ); 05 06 input [19:0]data_in; //需要移位比较数据输入 07 output [19:0]data_out; //移位比较完成数据输出 08 09 wire [3:0]bcd_reg2,bcd_reg3,bcd_reg1; //3次移位结果输出 10 11 //data_in[19:16]进行大四加三比较 12 cmp c1(.cmp_in(data_in[19:16]),.cmp_out(bcd_reg1)); 13 //data_in[15:12]进行大四加三比较 14 cmp c2(.cmp_in(data_in[15:12]),.cmp_out(bcd_reg2)); 15 //data_in[11:8]进行大四加三比较 16 cmp c3(.cmp_in(data_in[11:8]), .cmp_out(bcd_reg3)); 17 18 //data_in[19:8]全部比较完之后，左移一位 19 assign data_out={bcd_reg1[2:0],bcd_reg2,bcd_reg3,data_in[7:0],1'b0}; 20 21 endmodule |
第9行我们定义了3个位宽是4的寄存器，作用是存放比较之后的数据；第11~16行把cmp模块例化了3次，我们把输入数据的高12位分成3组分别送进了这3个例化模块的输入端口，作用是进行大四加三的调整；第19行将第12行~16行输出的数据存放到输出寄存器中进行一次左移操作。
cmp模块的代码如下：
| /**************************************************** * Engineer : 梦翼师兄 * QQ : 761664056 * The module function : 大四加三处理模块 *****************************************************/ 01 module cmp( 02 cmp_in, //比较器数据输入 03 cmp_out //比较器数据输出 04 ); 05 06 input [3:0]cmp_in; //比较器数据输入 07 output reg [3:0]cmp_out; //比较器数据输出 08 09 always @ (*) 10 begin 11 if (cmp_in > 4) 12 cmp_out = cmp_in + 3; //输入数据大四加三处理 13 else 14 cmp_out = cmp_in; //输入数据小于四不做任何处理 15 end 16 17 endmodule |
这个模块挺简单的，第9~15行只是将输入的数据和4进行了比较，大于4输出就是输入数据加三，小于4输入数据不做任何处理直接输出即可。
编写的测试代码如下：
| 01 `timescale 1ns/1ps //仿真时间单位是ns，仿真时间精度是ns 02 module bcd_tb; 03 04 reg [7:0]bin; //仿真激励二进制输入数据 05 06 wire [11:0]bcd; //仿真输出BCD码 07 08 bin_to_bcd u1(.bin(bin),.bcd(bcd)); //把激励信号送进BCD转换器 09 10 initial begin 11 bin=8'b0; //bin信号初始化 12 #100 bin=8'b1010_1101; //输入数据 173 13 #100 bin=8'b0000_1101; //输入数据 13 14 #100 bin=8'b1010_0100; //输入数据 164 15 #100 bin=8'b1000_0000; //输入数据 128 16 #100 bin=8'b1111_1111; //输入数据 255 17 end 18 19 endmodule |
仿真分析
如图所示，输入数据bin（无符号十进制表达）的值等于bcd（十六进制表达）输出的值，所以本次设计是成功的。