EDITORIAL words
Reduction operator is unary operator, but also with a NOR operation. Which is similar to the operation rule or bitwise operators and non-operation rules, but for different operational procedures. Bit operation is the corresponding bit of the operand with a NOR operation, the operand is a result of the operation is a few number of several digits. Curtailed operation is different, reduce the number of arithmetic operations is performed with a single non-recursive operation, the final result of the operation of a binary number. Calculating the reduced specific operation process is as follows: a NOR operation with a first and a second bits of the first operation of the first step, the second step of the operation result with the third NOR operation, and so on, until the last bit. E.g:
reg[3:0]B;
reg C;
C=&B;
Equivalent to
C=((B[0]&B[1])&B[2])&B[3];
Projects
Below, senior wing dream for everyone to write an example to validate the simulation waveform calculation result is, as we say. Integrated module code can be as follows
| /**************************************************** * Engineer: Dream Brother Wing * QQ : 761664056 * The module function: reduced sentence calculation module *****************************************************/ 01 module reduce(clk,rst_n,c); 02 the INPUT CLK ; // system clock input 03 the INPUT rst_n ; // reset 04 05 Output REG C ; // Output Register Definition 06 07 REG [ . 3 : 0 ] B ; // internal register defined 08 09 always@(posedge clk or negedge rst_n) 10 begin 11 if(!rst_n) 12 begin 13 c<=0; 14 B<=4'b1111; 15 end 16 else 17 begin 18 c<=&B; 19 end 20 end 21 22 endmodule |
Write test code as follows
| /**************************************************** * Engineer: Dream Brother Wing * QQ : 761664056 * The module function: reduced sentence test module *****************************************************/ 01 `timescale 1ns/1ps 02 module tb; 03 reg clk; 04 reg rst_n; 05 06 wire c; 07 08 initial 09 begin 10 clk=0; 11 rst_n=0; 12 # 1000.1 rst_n=1; 13 end 14 15 always #10 clk=~clk; 16 17 reduce reduce( 18 .clk(clk), 19 .rst_n(rst_n), 20 .c(c) 21 ); 22 endmodule |
查看仿真波形如下：
通过该波形可以看出，当变量B的四个位全部为高时，由于是“逻辑与”的运算，所以最终输出的变量C为高电平。
那么如果我们在变量B中加入一个零，结果会如何呢？我们仿真如下：
可以看到，如果变量B中存在零，那么输出结果由于“逻辑与”会得到低电平。