Embedded technology base and Practice - Learning Notes (a)

Embedded technology base and Practice - Learning Notes (a)

Architectural Overview Introduction KL series MCU and system

The series is based on the industry's first (ARM \ Cortex-M0 + \ ) \ core \ (the MCU \) , ultra-low power consumption, easy application design, scalability, and full range series and so on. \ (KL \) Series \ (the MCU \) Household appliances for portable medical system, smart meters, lighting, power supply, motor control and industrial control systems. \ (KL \) the main features of the series are as follows maximum operating frequency \ (48MHz \) , supports direct memory access \ (DMA \) , bit manipulation engine \ (BME \) , single-cycle access to the kernel memory speeds up to \ (1.77CoreMark / MHz \) , single-cycle access \ (I / O \) , the peripheral speed than the standard key \ (I / O \) maximum increase \ (50 \% \) ; \ (2 \) stage pipeline design reduced instruction number of cycles \ (the CPI \) , to improve the jump instruction and execution \ (the ISR \) interrupt service routine speed; and \ (8 \) bit, \ (16 \) bit \ (the MCU \) compared to a more streamlined code density, reducing \ (Flash \)Space, and power consumption of system resources; access to the program to optimize storage space more streamlined command system, fully compatible with \ (ARM \ Cortex-M0 \) , compatible \ (Cortex-M3 / M4 \ ) instruction set collection.

KL series MCU type designation

KL series MCU architecture overview

\ (KL \) Series \ (the MCU \) is \ (the AMBA \) bus specification as a system on chip architecture, as shown:

KL25 series memory map and interrupt sources

KL25 series memory map

The so-called image stored here can be intuitively understood as \ (M0 + \) addressed \ (4GB \) address space \ ((0x000 \ _0000 \ sim 0xFFFF \ _FFFF) \) is how to use, which corresponds to the actual physical media. The following use \ (GPIO \) to illustrate concepts related modules.

\ (The GPIO \) module uses the \ (0x400F \ _F000 \ sim 0x400F \ _FFFF \) address space , in these spaces \ (the GPIO \) registers \ (the CPU (i.e., M0 + core) \) internal registers (e.g., \ (R0, R1 \) etc.), the access \ (the GPIO \) registers must be accessed using direct address, that is to say requires three bus (address bus, data bus, a control bus). The access \ (CPU \) internal registers do not need to go through three bus (assembly language directly \ (R0, R1 \) and other names can be), no problem with the address. Because Access \ (the CPU \) internal register without passing through three bus, than accessing \ (the GPIO \) register fast . To distinguish between \ (the CPU \) internal register, \ (the GPIO \) register is also known as "shadow registers" \ ((the Mapping \ the Register) \) , corresponding to the address referred to as "image address" \ ((the Mapping \ the Address ) \) . The entire addressable space is directly referred to as "image address space" \ ((the Mapping \ the Address Space) \) .

For this table, remember that the main chip \ (Flash \) in the area and chip \ (RAM \) area for storing images. Because the interrupt vector code, in constant on-chip \ (Flash \) , the link source file after compiling and linking phase is required to be contained in the target chip \ (Flash \) information such as addresses the scope and purpose of the order successfully generate machine code. Link file needs to contain \ (the RAM \) information and address range of use and the like, in order to generate machine code exact location of global variables, and the stack pointer address of the static variable.

\ (KL25 \) chip \ (the Flash \) size \ (128KB \) , the address range is \ (0x0000 \ _ \ SIM 0x0001 \ _FFFF \) , are generally used to store interrupt vector code, constants , of which the first \ (192B \) for the interrupt vector table.

\ (KL25 \) chip \ (the RAM \) is a static random access memory \ (the SRAM \) , the size of \ (16KB \) , the address range \ (0x1FFF \ _F000 \ SIM 0x2000 \ _2FFF \) , generally used storing global variables, static variables, temporary variables (stack space) and so on.

KL25 interrupt sources

Interrupts are an important development of computer technology, it appears largely liberated processors, improve the efficiency of the processor. The so-called interruption means \ (MCU \) during normal operation of the program, since (MCU \) \ kernel exception or \ (MCU \) modules request event, causing \ (MCU \) stop running programs, and turn to handle exceptions or perform procedures to deal with external events.

Mainly refers to abort kernel interrupt, non-maskable interrupt, also known as the kernel interrupt, such interrupt by programming control, turn on or off the interrupt.

Interrupt vector number is a fixed number for each interrupt source, the decision is generated by the chip design, programming can not be changed, which represents the interrupt service routine entry address in the interrupt vector table position. \ (IRQ \) interrupt number is non-kernel interrupt source number, each number represents a non-kernel interrupt source.

KL25 pin function

\ (The MCU \) The minimum hardware means comprises a power system, crystal, reset, writing to the debugger interface allows the internal program is run, the specification, the core member may be multiplexed system. Circuit type requires a lot of pins are used to provide power sufficient current capacity while maintaining chip current balance, all the pins must be connected to a suitable power supply filter capacitor to suppress high frequency noise.

The minimum system hardware pin

GPIO and procedural framework

-Class I / O

The so-called universal \ (the I / O \) , also referred to as \ (the GPIO (General \ Purpose \ the I / O) \) , i.e., basic input / output, sometimes called parallel \ (the I / O \) , or normal \ (the I / O \) , it is \ (I / O \) is the most basic form. As a general purpose input pins, \ (the MCU \) internal program via the port register acquiring state of the pin . As a general purpose output pin, \ (the MCU \) internal program via port register state of the pin control .

A pull-down resistor is substantially connection

Port Control Module

\ (KL25 \) most pins having multiplexed functions can be provided by the register programming port control module which is designated for a specific function.

\ (PORT \) block contains three registers, namely, pin control registers \ ((Pin \ Control \ the Register) \) , the global control registers pin \ ((Free Join \ Pin \ the Register Control) \) , interrupted status flag register \ ((Interrupt \ the status \ In flag \ the register) \) .

\ (KL25 \) chip \ (5 \) ports \ (A \ SIM E \) , each port has \ (32 \) pin control registers \ (the PORTx \ _PCRn \) (where \ (X a = \ E SIM, n-= 0 \ SIM 31 is \) ), two global control registers pin \ ((the PORTx \ _GPCLR, the PORTx \ _GPCHR) \) , a status interrupt flag register \ (the PORTx \ _ISFR \) .

Pin Control Registers

Pin multiplexing control field, which determines what kind of pin multiplexing functions.

Each port has \ (32 \) pin control registers \ (the PORTx \ _PCRn \) . Port \ (X \) each pin control register \ (the PORTx \ _PCRn = \) \ (= 4004 \ _9000 + X \ + n-times1000 \ Times. 4 (X = A \ SIM E, corresponding to 0 \ sim 4, = 0 n-\ SIM 31 is) \) .

Wherein, \ (X-\) represents the state after reset uncertain. The following instructions given function, or unspecified bit reserved field (read-only, the value \ (0 \) ).

\ (D24 (the ISF) \) - interrupt status flag (read-only). Digital pin active mode . \ (The ISF = 0 \) , the interrupt pin is not detected; \ (the ISF. 1 = \) , detected by an interrupt pin. By write \ (1 \) , it is clear interrupt status flag. If the pin is configured as \ (the DMA \) request mode, completion \ (the DMA \) after the transmission request, it will automatically clear the interrupt status flag. If the pin is configured as a level-triggered interrupts, if the cause of the interruption level has been effective, the flag remains set, will be set immediately after even if they are clear.

\ (D19 \ D16 the SIM (IRQC) \) - interrupt configuration (read / write). Digital pin active mode . \ (0000 IRQC = \) , to close the interrupt pin \ (/ DMA \) request; \ (SIM IRQC = 0001 0011 \ \) respectively corresponding to the rising edge, falling edge transition, triggered \ (the DMA \) request; \ (0100 \) reserved; \ (1000 SIM 1100 is \ \) respectively corresponding to the logic low level (logic \ (0 \) ), a rising edge, falling edge transition, a high level (logic \ (1 \) ), triggers an interrupt pin. Other values are reserved. Special Note: Not all \ (KL25 \) pin can be configured as an interrupt function, only \ (A, D \) port pins have the above-mentioned interrupt this function .

\ (D10 \ the SIM D8 (MUX) \) - pin multiplexing control (read / write). Not all pins are multiplexed pin support slot. \ (The MUX 000 = \) , pin is not configured (analog pin); \ (the MUX 001 = \) , general purpose input output pins as \ ((the GPIO) \) function; \ (= the MUX 010 \ SIM 111 \) , are arranged for the first function pin \ (2 \) to the second \ (7 \) functions (the functions for the chip reference manual \ (10.3 \) section).

\ (D6 (DSE) \) - drive capability enable bit (read / write). Table name is configured to drive the pin when the digital output capability condition, effective digital mode pin . \ (The DSE = 0 \) , low drive capability; \ (= the DSE. 1 \) , a high driving capability. From the data sheet \ (KL25 \) low drive capability is \ (5mA \) , high drive capability is \ (18mA \) . But not all pins can be configured as a high drive capability.

\ (D4 (PFE) \) - passive filter enable bit (read / write). Digital pin active mode . \ (The PFE = 0 \) , the corresponding pins prohibited passive input filter; \ (= the PFE. 1 \) .

\ (D2 (SRE) \) - Conversion Rate Enable bit (read / write). Digital pin active mode . \ (0 \) - pin is configured as fast slew rate. \ (1 \) - pin is configured as a slow slew rate.

\ (Dl (the PE) \) - pullup or pulldown enable bit (read / write). Digital pin active mode . \ (0 \) - pull-down resistor on the corresponding internal pin closed; \ (1 \) - pullup or pulldown resistor is enabled respective inner pin, most digital input pin.

\ (D0 (PS) \) - pull-up or pull-down selection (read / write). Digital pin active mode . \ (The PS = 0 \) , if the \ (PE = 1 \) , enable pull-down resistor pin; \ (the PS. 1 = \) , if the \ (PE = 1 \) pull-up resistor, the pin is enabled. \ (KL25 \) pull-down resistor internal size of \ (20 is \ 50K SIM \ Omega \) .

Global control registers pin

Each port has two global control pin register for write-only register . Global control register pin (low) \ (the PORTx \ _GPCLR \) , the address \ (= 4004 \ _9080 + X \ Times 1000 \) ; pin global control register (high) \ (the PORTx \ _GPCHR \) , the address \ ( 4004 = \ _9084 + X \ Times 1000 \) .

Each register is high \ (16 \) bits are called global write enable pin field \ (GPWE \) , low \ (16 \) bit write data is called a global pin field \ (GPWD \) . If \ (GPWE = 0xFFFF \) , then \ (GPWD \) field \ (16 \) bit is written to a control register of the entire group of pins low \ (16 \) bits.

Interrupt status flag register

Each port has an interrupt status flag register \ (the PORTx \ _ISFR \) , the address \ (= 4004 \ _90A0 + X \ Times 1000 \) .

Mode the digital pins, each pin can be independently configured interrupt mode, the pin control register \ (IRQC \) field may be configured to select.

Interrupt flag register of each port, the port should be of the \ (32 \) pins, corresponding to \ (1 \) , it indicates that the configuration of the interrupt has been detected, not vice versa. You have to write \ (1 \) cleared \ (0 \) characteristics.

GPIO module - External and internal register pin

\ (80 \) pin package \ (KL25 \) chip \ (the GPIO \) pins into \ (5 \) ports, labeled \ (A, B, C, D, E \) , containing a total of \ (61 \) pins.

Each \ (the GPIO \) ports are \ (6 \) registers, \ (5 \) a \ (the GPIO \) port shared \ (30 \) registers. \ (A, B, C, D, E \) Each port register base address are \ (400F \ _F000h, 400F \ _F040h, 400F \ _F0080h, 400F \ _F0C0h, 400F \ _F100h \) , so that each port group address difference \ (40H \) . \ (= The PORTx 400F \ _F000 + X \ Times 40 \) . Each register has \ (32 \) bits corresponding to \ (32 \) pin input and output mode.

GPIO basic programming steps

1. Control registers Port Pin Control Module \ (PORTx \ _PCRn \) pin multiplexed field \ ((the MUX) \) is set as \ (the GPIO \) function (and even if \ (= the MUX 001 \) ).
2. By \ (the GPIO \) corresponding port module "data direction register" to specify the corresponding pin is an input or output functions. If the specified bit is \ (0 \) , then the corresponding pin is an input; if the specified bit \ (1 \) , the corresponding output pin.
3. If the output pin, an output pin corresponding to the specified low or high by setting "the data output register." It may also be implemented by other register.
4. If access pins, the "data input register" is obtained by a pin.