How the signal sequence (or virtual monitoring of DUT sequence - a total which methods can be achieved?
To answer this question, you need to have a real project experience, can be used as face questions, interview junior engineer, you can view his technical skills.
The first method: built-in functions provided by uvm uvm_hdl_read, backdoor access (static), and implemented together with a do while.
For example, in reference to the following code sequence can realize the function:
logic dma_req_r;
do begin
uvm_hdl_read("hw_top.DUT.dma_req",dma_req_r);
#200ns;
end while(dma_req_r !=1)
the first method:
The second method:
The third method:
The fourth method: