Hass Hi3716M translation and definition broadcasting low-end IPTV solution components Introduction

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Hi3716M is a dedicated low-end to high-definition broadcasting translation and IPTV build the chip can meet the requirements of high-definition set-top box translation, can be applied to high-definition multimedia playback. Hi3716M using ARM 's advanced Cortex A9 processor architecture, 1500DMIPs processing power to meet the business needs of digital cable TV.

Hi3716M the built-in 2 -channel Ethernet and 2 -way USB interface, providing flexible connectivity solutions. Support MPEG2 / H.264 / AVS variety of formats such as HD video decoding, meet the requirements of multimedia playback.

 

CPU

l performance ARM Cortex A9 processor

l provides 1500DMIPs processing capability

the 内置I-cache , D-cache , L2 cache

l Hardware JAVA acceleration

l support for floating-point coprocessor

 

The memory control interface

L DDR2 / DDR3 Interface

- maximum support 512MB

- memory bit width 32 / 16bit

l Support SPI Flash

- maximum support 2 Pian SPI Flash

- Monolithic maximum capacity of 16MB

l Support NAND Flash

- Support SLC / MLC devices

- Support 8bit of eMMC interfaces

Video decoding

l H264 MPHP@ level 4.1

l Support MPEG1

l support MPEG2 MP @ HL

l Support MPEG4 SP @ L0-3 , ASP @ L0-5

l support DivX4 ~ . 6

l Support AVS standard grade @ Level 6.0

l Support 1080p ( 30fps ) in real-time decoding capabilities

l after denoising support and deblocking video processing such as

Picture decoding

l support JPEG decoding, up to 6400 megapixels

l support PNG decoder

Audio and video encoding

l supports H.264 / MPEG-4 video coding, up to a maximum resolution D1

l Support JPEG encoding

l The video encoding bit rate and fixed rate provides dynamic pattern

l Support 1 channel audio coding

l Support echo cancellation

The audio decoding

l Support MPEG L1 / L2 decoding

l supports two-way mix

l supports intelligent volume control

TS stream is demultiplexed / PVR function

l Support 2 digital TS stream input, one channel RF input

l built a path QAM module ( Annex A / C )

l support all the way QAM loopback output

l maximum support 96 hardware PID filters

l Support PVR recording

l support plus non-spoiler and spoiler plus recording

l supports AES / DES / 3DES data encryption process

l Support USB content protection equipment

Peripheral Interface

L 2 th the USB 2.0 the HOST (Integrated a PHY )

L 2 th 10M / 100M adaptive network port, providing 2 Layer 2 switching functionality

L . 3 th UART interfaces

L 2 th SmartCard interface, support T0 / T1 / T14 protocol

L . 1 th IR receiving processor that provides 2 input ports

L . 1 th LED and KeyPAD control interface

L . 3 th I2C interfaces

L 13 is set GPIO interfaces

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