Makefile macro definitions

Actually gcc -D command supports macro definitions, the equivalent of a global #define C:

gcc -D name
gcc -D name=definition

Makefile can define variables (and macros like), but it is to make the interpreter using, for the compiled file no effect.

 

MSTAR: macro definitions: definitions and values ​​define the way the way the string

CC_TVOPTS += -DMS_BOARD_TYPE_SEL=$(BOARD_TYPE_SEL)
CC_TVOPTS += -DMS_SW_CUS_SEL=SW_CONFIG_TRUNK_ATVMM
CC_TVOPTS += -DENABLE_CAPE=0 
CC_TVOPTS += -DMS_SW_TEST=\"VIDEOCON.BIN\"
CC_TVOPTS += -DMS_SW_TEST=\"${MEGENAME}\"

Keywords: Make macro definition macro definition transfer Make Makefile Makefile -D adding macro definitions

in the Makefile, we can compile the source code to control by the macro definition. As long as CFLAGS in the Makefile to specify in your macro can be defined by the option -D.

Such as:

CFLAGS + = -D _SAYHELLO 
at compile time to add this option on it: $ (CC) $ (CFLAGS ) $ ^ -o $ @

Here is what I wrote a test file:

E.g:

Makefile file contents:

CC = gcc
RM = rm

CFLAGS += -D _SAYHELLO

TARGETS := myapp

all:$(TARGETS)

$(TARGETS):main.c
$(CC) $(CFLAGS) $^ -o $@

clean:
-$(RM) -f *.o
-$(RM) -f $(TARGETS)

 

main.c文件的内容为：
#include <stdio.h>

int main()
{

　　#ifdef _SAYHELLO
　　　　printf("Hello , How are you?\n");
　　#else
　　　　printf("Sorry to lost you. \n");
　　#endif

　　return 0;
}

　　

Enter the make clean in all ports
and enter ./myapp

result Hello, How are you?