After the logical unit number of the program compiled for the FPGA 0

problem

After being given FPGA code compiler is not finished, the display using the number of logical units (Total logic elements) is zero. Of course, the program does not work.
I use the Intel Altera FPGA, verilog language, developed under Quartus.

the reason

Top module no valid output. For example, the output has no value or an output connected to the sub-modules, sub-modules problem.

If not properly set top module output, the compiler optimization, that no output module, or logic unit output without.
Example 1:

module test
(
input clk,
input rst,
output out1,
output out2,
output out3
);

assign out1 = clk;
assign out2 = ~clk;

endmodule

The clock signal output out1 directly, without making any treatment; OUT2 of the inverted output clock signal, only a NAND gate, a logic unit not required; out3 but without any treatment.
Thus the number of the above code is compiled logic unit 0 is obtained.

Example 2:

module test
(
input clk,
input rst,
input [3:0] data,
output out
);

reg [3:0] store [7:0];
reg [3:0] k;

always @ (posedge clk or negedge rst)
begin
    if (!rst)
        k <= 1'b0;
    else
    begin
        store[k] <= data;
        if (k == 4'd7)
            k <= 0;
        else
            k <= k + 1'b1;
    end
end

endmodule

Code looks to achieve a certain function, be sure to use the logical unit, right?
But in fact, no real top-level module output, the equivalent of your code do useless work, there are no results did not send out. After the compiler is still no logical unit.

Solution

Checking code associated with the top portion of the output module in particular, see the top module has a valid output.