Recurring problem
Closed graph problems
1, Max9218 accept data disorders.
Resolution process: The time associated interfaces, and a test clock signal line and field Lock , found Max9247 output clock and Max921 input clock mismatch.
Solution: are changed to 15M clock.
2, Max9218 the lock does not lock.
Resolution process: MAX9218 above record, under normal circumstances, should be the beginning of a low level, remained after locked 3.3v high. Here, not investigation, said they were there the last pre-board impedance mismatch.
3, Max9218 receives an image white point.
Resolution process: data found acceptable, the received data and the actual data sent over the lowest level there is always hopping and even received is not necessarily accurate data. Remove test input image (trellis diagram, FIG gradient) to the Dsp Image quality, we have found that white spots. Finally, look at collecting relevant local discovery Max9247 and Max9218 should be doing rising and falling edges match.
Solution: MAX9247 of the rising edge, MAX9218 falling edge reception.
4, because the image interference problems, leading to split-screen, and take a lot of detours. Because the law can not reproduce this phenomenon.
Resolution process : a field signal measured just beginning, the scene is a signal cycle. Pretreatment plate finally found to be a valid data clock cycle, the data is directly counted. I found each time the screen is split data valid signal and clock pre-board clock to inconsistent results in the line Analysis of the interference field signal disturbance.
Solution: add fault tolerance, because the DSP can not take the wrong map will cause image tracking error, meanshift algorithm needs to keep track of the target has been re-box. But you can throw chart. Therefore FPGA able to save a map, when a data amount of valid data is not correct, clear and reset the FIFO . Fifo reset time is greater than three clock cycles.
With Dsp communication mechanism.
1, every game's first eight byte is not written into it. srio finished doorbell is not pulled when TLAST .
2, Dsp initialization time is required, generally give Dsp before the onset of FIG, to confirm Dsp initialized state, by doorbell or Gpio embodiment.
3 , Dsp because disruptions, leading to not work as 20ms made plans, image jitter. Instead bram cache image, after verification, image output is generally not recommended to use the FIFO , because the image can not be guaranteed without interference. And when a large number of image cache, you should use DDR ping-pong buffer cache way.
The image output problem
1, parity field problems. FIG gradient made normal, but the actual image abnormality. Failed to understand the odd field, ADV7179 transmission mode is stored by the odd field blocks, odd and even fields of the interlaced output.
Resolution process: look at the analog video output document ( BT656 , BT601 ), verification for Adv7179 and FPGA operating mode should be FPGA to accept the normal image, but every game in the first to Adv7179 made odd field recurrence even field. (All odd lines in each field is continuously sent, and then send all even rows corresponding to the field). Failure to understand the concept of time field, because the analog video output is the first odd row, even in the output line, so I will understand. Resulting in image transmission errors, and I was always the amount of data to troubleshoot the problem.
Solution: After check documents aware of the problem, the parity sub-field receiver and then transmitted. Use FIFO to points odd and even field, signals are always allowed card, then authentication can not confirm. So let DSp parity field points. Next is the FPGA to do.
Parity field design ( FIFO ) : Proven, Dsp one packet per round, there will be more than ten intermediate clock cycle interval.
Provided at the receiving state machine, the state set the parity bit line, an initial value of zero bits. Each receives a packet ( 256bit ), the packet count by 1 . The output image, the odd lines starting, even after the hair line, the row parity status bit 0 of the odd lines, one for the even lines. Each row is 320. pixels, so every ten packets received, the parity bit is inverted by the line, the output of the flag, to set up two FIFO , when the status bit is 0 , the to fifo1 write, when the status bit . 1 , the to fifo2 write. In the output image, the odd field to fifo1 taken, on the even-numbered fields fifo2 taken.
Parity field design ( Bram ) : Set the line counter, each fully recorded 320 while pixels. Take zero. Furthermore the fully recorded each time the counter 320 when the pixel, taken address plus 320 . When the odd field, taking the address initial value 0x00 , when the even field, set fetch address 0x140 .
2, the register mode is selected according to the default configuration. At that time because Adv7179 is coded chip can support a custom image, and now need to configure two unknown to normal mode register output image reasons.
3, Adv7179 output is 720 * 576 , but only to the intermediate output 320 * 256 .
Solution: card pixels, wanted to match the corresponding parity line. Other bits zeros.
4, Iic configured incorrectly.
Lim brothers communicate with inflammation, Zynq the iic write address bits to the right one, set repead mode.
Check the signal
1 , the reason is not FIG.
(1) Check the enable signal (the amount of data is not satisfied), such as ADV7179 needs of each figure has a certain area and the video blanking active area, and if not not shown in FIG.
(2) measuring the output voltage data. Analog video data is output voltages 1.2V approximately. In the output data, the field signal is a negative level, only but obviously there is a high to low voltage and the data is not the same waveform is blanking area. After the addition of a push three data output wrong voltage, resulting in no data output.
(3) an output waveform diagram: comprising a peak, the clock frequency, the output frequency of the voltage data.
1, shaking FIG cause chaos in FIG.
(1) does not generally match the amount of data. The main problem will cause an abnormal image display output section. As the amount of data in which the error, need to rely on experience testing. Testing should generally start to finish to see whether a picture output can match the timing design.
(2) clock is not accurate. The main problem will lead to chaos flash the whole map, but also will become erratic.
(Due to computer updates, no test data)
To Do Content
1, sub-parity line.
2, plus preprocessing algorithm.