IIC bus generally have two signal lines SCL and the SDA;
Usually SCL and SDA are pull-up resistor by the solid line and the conversion level increasing the driving capability;
IIC bus protocol comprising: a start signal, stop signal, a data bit, acknowledge bit;
9 is a general communication CLK, 8 data bits plus one acknowledge bit;
IIC belongs synchronous communication, CLK signal lines are separate.
| TSU: STA | Former SDA Fall, SCL to maintain a high time |
| THD: STA | After the fall SDA, SCL to maintain a high time |
| TSU: DAT | Before rising SCL, SDA unchanged time |
| THD: DAT | After the fall SCL, SDA unchanged time |
| TSU: STO | Before rising SDA, SCL to maintain a high time |
Which, SDA can only change to the low level data in SCL;
IIC bus test read timing when you want to test TSU: DAT and THD: DAT on it. Because the START and STOP signals are emitted by the master device.
IIC bus test write timing when all the timing will need to be tested.
SCL frequency is generally configured according to a reference clock multiplier or divider.
The number of devices on the IIC bus by 400pf capacitive load limit.
Because in the RC circuit time constant τ = RC, if C is too large will cause the rise time of the clock square wave, square wave causes distortion, such as ringing signal quality problems, causes an increase in the error rate of data communication and reduce the communication quality .