Seven of the rear end of the new step, the text "front LLVM backend document analysis had been introduced" in the. "We are differences create a new LLVM back end of the first step in the document and code " and " Target Registration corrections " have been existing documents listed in the first step "Create a subclass of the TargetMachine class that describes characteristics differences of your target machine "and the actual code. Of course, the existing document is used as a back-end Sparc example, when I analyze the code used is RISCV back-end code. By contrast both a little awkward, but it does not affect the contrast. I plan after the back-end document analysis and comparison of series finished, a Chinese version can write to RISCV as an example of " Writing An LLVM Backend " document, there is a need to facilitate the students familiar with the back-end reading. I chose RISCV, but also because of the recent venture Masamori, and I personally optimistic about their development; at the same time, also can Sparc example of the original document forming the difference.
The second step of the rear end of the new document, the main contents are:. Describe the register set of the target introduce official document basically no problem, but some of the content of the document has not kept updated code. In doing this brief summary:
1, mainly the establishment of SparcRegisterInfo.td, SparcRegisterInfo.h and SparcRegisterInfo.cpp in llvm / lib / Target / Sparc / for the target platform.
2, in SparcRegisterInfo.td to be established subclass Register <n>:
class SparcReg<bits<16> Enc, string n> : Register<n> {After, to create an object of this class for each Sparc register. At the same time, but also to establish a series of objects in SparcRegisterInfo.td in RegisterClass class. The RegisterClass class of The (specified in Target.td ) Used to DEFINE AN IS Object Represents by that of Group A and Related Registers The Defines The default Also Allocation Order of The Registers. Therefore, objects of this class is associated to the expression of a set of registers and register allocation the default order.
In fact, Register and RegisterClass these two classes are in llvm / include / llvm / Target / Target.td defined in.
3, SparcRegisterInfo.h and SparcRegisterInfo.cpp implementation. These two documents is mainly to achieve some manual RISCVRegisterInfo class code, which is a subclass of SparcRegisterInfo.td RISCVGenRegisterInfo generated file:
struct RISCVRegisterInfo : public RISCVGenRegisterInfo {So, in addition to some members SparcRegisterInfo.h direct function can return values, but also overloaded in SparcRegisterInfo.cpp some functions, document describes the need to reload functions are:
- getCalleeSavedRegs — Returns a list of callee-saved registers in the order of the desired callee-save stack frame offset.
- getReservedRegs — Returns a bitset indexed by physical register numbers, indicating if a particular register is unavailable.
- hasFP — Return a Boolean indicating if a function should have a dedicated frame pointer register.
- eliminateCallFramePseudoInstr — If call frame setup or destroy pseudo instructions are used, this can be called to eliminate them.
- eliminateFrameIndex — Eliminate abstract frame indices from instructions that may use them.
- emitPrologue — Insert prologue code into the function.
- emitEpilogue — Insert epilogue code into the function.
In this session, documentation and code there are some differences, the document does not keep up with the actual code to update the contents of the code can be found in: SparcRegisterInfo.cpp .
In RISCV rear end, the front face 2 and also consistent with the document, but the content of the specific features RISCV replaced. But RISCV latest code on this step, too, and documents are quite different, actually overloaded member functions implemented as follows:
const uint32_t *getCallPreservedMask(const MachineFunction &MF,
CallingConv::ID) const override;
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
BitVector getReservedRegs(const MachineFunction &MF) const override;
bool isConstantPhysReg(unsigned PhysReg) const override;
const uint32_t *getNoPreservedMask() const override;
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;
unsigned getFrameRegister(const MachineFunction &MF) const override;
See specific code RISCV: RISCVRegisterInfo.h , RISCVRegisterInfo.cpp and RISCVRegisterInfo.td .
Overall, the difference between documentation and code of this part is not mainly differ in part 3 of the overloaded member function, and this difference does not affect the understanding of the documentation and code. Accepted more than the difference better than before.
References: Writing AN LLVM Backend
Reference Code: LLVM / LLVM-Project Latest the commit 9ed325e
related information:
Little angel his father: LLVM daily talk of thirty-seven LLVM backend Profile (Hangzhou Share PPT)
Little angel his father: LLVM daily talk of forty-seven LLVM backend document parsing
Little angel his father: LLVM talk about the daily forty-eight LLVM backend document parsing 1
Little angel his father: LLVM talk about the daily forty-nine LLVM backend document parsing 2
Little angel his father: LLVM daily talk of fifty-one TargetMachine
Little angel his father: LLVM talk about the daily fifty-three Target Registration Correction
Edited on 2019-06-03