MT47H64M16NF-25EM-related parameters introduced
Wherein
· Vop = + 1.8V ± 0.1V, + 1.8V ± 0.1V = VDDO
· the JEDEC standard 1.8V1 / O (SSTL_18 compatible)
and difference data strobe (DQS, DQS #) option
· 4N bit prefetch architecture
· x8 repetition strobe output (the RDQS) option.
· DLI DQ and DQS conversion will be aligned with the CK
-8 while internal bank operations
Programmable CAS latency (CL)
· CAS issued an additional delay (AL)
· WRITE latency = READ -1CK delay
· MT47H64M16NF-25EM: HTTP: // www.dzsc.com/ic-detail/9_7568.html
· optional burst length (BL): 4, or 8
-adjustable data output drive strength
· 64ms, 8192 cycle refresh
terminal (ODT) on-chip
-industrial temperature ( IT) option
· RoHS compliant
· supports JEDEC clock jitter specifications
Options
* Configuration
-256Meg × 4 (32 Megx4x8 group) 256M4
-128 Megx8 (16 Meg Bank x8x8) x16 128M8-64Meg (MEGX. 8. 8 × 16 Bank) 64M16
· FBGA package (unleaded) -x16
-84-Ball FBGA (8mmx12.5mm) Rev.GH the HR
· FBGA package (Lead) -. 4 ×, x8
-60-Ball FBGA (8mmx11.5mm) HQ rev.G
· FBGA package (Lead) -. 4 ×, x8
-60- FBGA Ball (8mmx 10mm) CF are Rev.H
· FBGA package (lead solder) -x16
-84-Ball FBGA (8mmx12.5mm) Hw rev.G, H
· FBGA package (lead solder) -. 4 ×, x8
-60 - ball FBGA (8mmx11.5mm) rev.G the HV
· FBGA package (lead solder) -X4, x8
-60-ball FBGA (8mmx 10mm) ReV.H of JN br /> · timed cycle time
-1.875ns@CL=7 (of DDR2-1066) -187E
-2.5ns@CL=5 (DDR2-800) -25E
-2.5ns@CL=6 (DDR2-800) -25-3.0ns = order. 4 CL (DDR2-667) -3E br />-3.0ns@CL=5(DDR2-667)-3-
-3.75ns@CL=4 (DDR2-533) -37E
· Self-Refresh - StandardNone
- low battery
Operating temperature
- Business (0 "℃ ≤Tc≤85 '℃) None
- Industry (sTc595'GrT deg.] C -40 [deg.]
-40 deg.] C ≦ T / ≤ 85 deg.] C) - Automotive (-40 '℃ STC, TAS1050C) AT
Reproduced in: https: //blog.51cto.com/14236986/2404885