In an actual synchronous digital system, the data must be sampled at the clock pulse edge arrives. The shortest time needed to achieve this goal is called "settling time."
In addition to reaching the outer edge of the first clock pulse, the data must be maintained for a certain time clock edge, this time is called "retention time." Retention time may be negative, in this case the end of the data already before reaching the clock edge; may be zero, this time to keep the data sampling clock edge; may be a positive, this time to keep the data sampling clock edge is completed after a period of time.