Floating-point arithmetic in the FPGA implementation - Scaling, FPGA floating point

Some of the FPGA can not directly operate on floating point numbers, using only fixed-point numerical computation. For FPGA, participation in math book is 16-bit integer, but if how to do math in decimal it appear? You know, FPGA is powerless to decimal, one solution is to use calibration. Scaling the number of floating point operation is to be enlarged many times, and then rounded, and then calculates the number, the result of the operation and then reduced to give the corresponding multiple of it. In the design, we must not forget the decimal point. In the FPGA is not manifest the decimal point, the decimal point position only programmers know. Q represents a decimal point, Q15 represents a decimal point to the first 15.

Float (x) is converted to fixed point (xq): xq = (int) x * 2 ^ Q

Fixed point (XQ) converts floating point (x): x = (float) xq * 2 ^ (- Q)

For example, the hexadecimal number 2000H, is expressed by Q0 8192; if expressed by Q15, was 0.25.

Here Q format determined Q value calculation:

(1) fixed-point addition and subtraction: Q format needs to be converted to the same acceleration

(2) point multiplication: multiplying the data in different formats Q, Q value corresponding to the sum

(3) fixed point division: dividing data in different formats Q, Q value corresponding to a subtraction

(4) pointing to the left: the equivalent Q value increases

(5) pointing to the right: the equivalent Q value decreases

For example, 4000H (floating-point number 0.5) is multiplied by a Q15 Q15 represented by 4000H, 4000H × 4000H = 1000 0000H, Q value after completion changed by 15 + 15 = 30, i.e., the result is to 0.01 B, 0.25 is the float.

 

fpga how floating-point operations

The floating-point number multiplied by 2 ^ n, and replaced with integer calculation, the final narrowing. We can only be approximately.
 

FPGA aid, implemented using floating-point number verilog

DSP decimal format is what. It is a fixed-point or floating-point format. If the fixed-point number, can be fixed by the FPGA IP core converts the floating-point turn, then floating-point calculations IP core call on the line, floating-point arithmetic calculations.

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Origin blog.csdn.net/l471094842/article/details/90812553