Table of contents
1. Where in the cache (cache memory) are the blocks in the main memory placed?
Fully associative mapping: blocks in main memory are placed in the cache at will (that is, they can be placed in any row in the cache)
Direct mapping: How many rows does the main memory block number % cache have? The result calculated in this way is the location where the main memory block is stored in the cache.
Group connection mapping: How many groups are there in the main memory block number %cache? The result calculated in this way is the group in which the main memory block is stored in the cache. As for the group, it can be placed at will.
2. What are mark bits, valid bits, and hits?
2.1 Mark bit
Mark bit = main memory block number. When something in the main memory block is placed in the cache, the corresponding main memory block number will be set as the mark bit. In this way, the next time the CPU wants to access the main memory at this location, it does not need to directly access the main memory, it can only be found in the cache.
For example: if the CPU wants to access address A in the main memory, it will first check to see if there is A in the cache. Since address A is placed in the cache, it can just look for the cache directly without going to the main memory. bingo.
The specific process during this period is like this. The CPU first finds the mark bit in the cache. After finding the mark bit, it finds the corresponding cache line, and then passes The address within the block finds the corresponding location in the corresponding cache line.
(Main memory address A = main memory block number + block address)
2.2 Valid bits
Lines that do not put anything in the cache will be set to 0 by default. At this time, there may be many 0s, and if the main memory block number 0 is placed in the cache, it will be confused with it, so the concept of valid bits is introduced. After putting it in, the valid bit is set to 1, and if it is not put in, it is set to 0. In this way, even if the main memory block number 0 is put, there will be no confusion.
2.3 hits
What does hit mean? My personal understanding is: the CPU finds what it wants to find in main memory in the cache. If it is not found in the cache, it is a miss. If there is a miss, the CPU needs to access the main memory. Although this will be slower, there is no way. After all, it is not in the cache, so it can only go to the main memory to find it.
3. Fully associative mapping
This is a screenshot from Wangdao's postgraduate entrance examination. If you are interested, you can read Wangdao's explanation.
Link: https://pan.baidu.com/s/1dkDtZxbSP0OHvJDaoKR5rg Extraction code: ngc1
Note here: 1MB = 210 KB = 220 B
So 256MB = 228 B
And because each row The length is 64B = 26B
, so the cache block address is 2 6
Because the size of the cache block is equal to the size of the main memory block, that is, the size of each row of the cache and the main memory is equal, so the address in the main memory block is 6 bits a>
228/26 = 222
So the main memory block number is 22 bits
4. Direct mapping
A big disadvantage of direct mapping is that it can only be placed in a fixed position and has poor flexibility, which will make large areas of memory unable to be fully utilized.
For example, as shown in the picture, the main memory block number 8 should be placed in the cache, corresponding to the row of 0, but other places are obviously empty, but are not used, and are placed When it reaches 0, will overwrite the original .
4.1 Optimize mark bits
The last three digits of the main memory block number correspond to the binary number of the row number in the cache.
After optimization here, the number of mark bits can be reduced by 3 digits. In fact, subdivides the main memory block number. Mark bits and line numbers are separated.
5. Group connection mapping
6. After-class exercises
Assume that the main memory capacity of a computer is 4MB, the Cache capacity is 16KB, each block contains 8 words, and each word is 32 bits. Design a 4-way group connected image (that is, there are 4 blocks in each group of Cache). Cache organization, requirements:
(1) Draw the number of digits in each field in the main memory address field
(2) Assume that the initial state of the Cache is empty, and the CPU Read 100 words from units 0, 1, 2,..., 99 of the main memory in sequence (the main memory reads one word in sequence), and repeat reading in this order 8 times. What is the hit rate?
(3) If the speed of Cache is 6 times that of main memory, how many times is the speed increased with Cache compared with without Cache?
Examples about main memory addresses
Detailed explanations about main memory addresses
After reading these two articles, let me ask the first question It should be easier.
(1) Main memory address = area number + group number + block number within the group + address number within the block
Because the Cache capacity is 16KB, that is, 214 B, each B (byte) contains 8 bits< a i=3> Cache capacity = 16KB/(8*32) bits = (214*8)/28 = 29blocks and because every 4 blocks are in a group , so there are 29/4 = 27 groups, through binary To represent 27 group, so 7 bits are needed, so the group number is 7. (For the 21 group, 1 binary digit is required, 0 and 1; 22 Group = 4 groups, you need 2 binary digits, 00 = 0, 01 = 1, 10 = 3, 11 = 4)
The block number in the group refers to how many blocks there are in a group. Here it is a group of 4 blocks, which is a group of 22, so it is converted to Binary requires two bits, so block number within group = 2
If not explicitly specified,defaults to byte addressing, then each word is 32 bits/8 = 4 bytes , and because each block contains 8 words, a block has 8*4 = 32 bytes = 25 bytes
Therefore, the address number in the block = 5
Because the main memory capacity is 4MB = 222 B, the main memory address has a total of 22 bits
Finally, area code = 22 - 7 - 2 - 5 = 8
The main memory address format is as follows:
| area code | Group No | Block number within group | address within block |
|---|---|---|---|
| 8 bits | 7 bits | 2 people | 5 people |
(2) Since each word block has 8 words, main memory units 0, 1, 2,..., 99 are respectively in 0~12, and are mapped to groups 0 to 12 respectively using four-way group connection. However, since the Cache is initially empty, when reading for the first time, the first unit of each block read is empty and there is no hit, but every unit can be hit in the next 7 times.
Hit rate = (100-13 + 7x100) / 8x100 = 98.4%
(3) Assume the access cycle of Cache is T, then the access cycle of main memory is 6T.
Access time with Cache = H × Tc + (1 - H) × (Tm + Tc) = Tc + (1 - H) × Tm = T + (1 - 98.4%) × 6T= 1.096T