[LittleXi] C program preprocessing, compilation, assembly, and linking steps

[LittleXi] C program preprocessing, compilation, assembly, and linking steps

C program

#include<stdio.h> 

int main(){
    
    
    int x=1,y=1;
    printf("x+y=%d",x+y);
}

1. Preprocessing

Import header files, remove comments, and decentralize macro definitions

Execute instructions

g++ -E esc.c -o esc.i

2. Compile

Compile the processed code into assembly code.s

Execute instructions

g++ -S esc.i -o esc.s

3. Compilation

Convert the compiled .s file into machine code .o

Execute instructions

g++ -c esc.s -o esc

4. Link

• Linking is the process of combining multiple object files and library files into a final executable file.
• The linker (such as the GNU linker, often calledld) performs this process to resolve the symbolic reference relationships between different object files and connect them together.
• The main tasks include parsing symbol references, symbol resolution, symbol relocation, and generating executable files.
• If external libraries (such as the standard C library) are used, the linker will also link the required library files with the program to satisfy the program's dependencies.

Execute instructions

g++ esc.o -o esc

5. In addition, you can also write your own Makefile. The example is as follows

documentmain.c

// main.c
#include <stdio.h>
#include "library.h"

int main() {
    
    
    int result = add(3, 5);
    printf("Result: %d\n", result);
    return 0;
}

documentlibrary.h

// library.h
#ifndef LIBRARY_H
#define LIBRARY_H

int add(int a, int b);

#endif

documentlibrary.c

// library.c
#include "library.h"

int add(int a, int b) {
    
    
    return a + b;
}

Makefiledocument

CC = g++
CFLAGS = -Wall -std=c++11
SRC = main.cpp library.cpp
OBJS = $(SRC:.cpp=.o)
TARGET = main

all: $(TARGET)

$(TARGET): $(OBJS)
	$(CC) $(CFLAGS) $^ -o $@

%.o: %.cpp
	$(CC) $(CFLAGS) -c $< -o $@

clean:
	rm -f $(OBJS) $(TARGET)

.PHONY: all clean

explain

1. CC = g++：
   • This line defines a Makefile variable CC, which specifies the name of the C++ compiler. In this example, we use g++ as the C++ compiler.
2. CFLAGS = -Wall -std=c++11：
   • This line defines a Makefile variable CFLAGS, which contains compilation options. -Wall means to enable all warnings, -std=c++11 specifies the C++11 standard.
3. SRC = main.cpp library.cpp：
   • This line defines a Makefile variable SRC, which contains the names of all source files of the project.
4. OBJS = $(SRC:.cpp=.o)：
   • This line defines a Makefile variable OBJS, which is a list of target files for all source files in SRC. The .cpp file extension is replaced with the .o file extension.
5. TARGET = main：
   • This line defines a Makefile variable TARGET, which represents the name of the final executable program.
6. all: $(TARGET)：
   • This is a Makefile rule, indicating that all is the default target. When you run the make command, it will build $(TARGET).
7. $(TARGET): $(OBJS)：
   • This is a Makefile rule that defines how to build an executable program from an object file. $(OBJS) means depending on the target file list. The command $(CC) $(CFLAGS) $^ -o $@ in the rule compiles the object file using the g++ compiler and links it into an executable program.
8. %.o: %.cpp：
   • This is a Makefile rule that defines how to compile each source file into the corresponding target file. %.o represents all target files, %.cpp represents the corresponding source files. The command $(CC) $(CFLAGS) -c $< -o $@ in the rule compiles each source file into the corresponding target file.
9. clean：
   • This is a Makefile rule used to clean generated object files and executable programs. Command rm -f $(OBJS) $(TARGET) deletes target files and executable programs.
10. .PHONY: all clean：
    • The line tells the Make tool that all and clean are pseudo-targets and do not represent actual files, so their timestamps will not be checked. This ensures that make always executes both targets without interference from file timestamps.