Table of contents
Summary
DC-DC BUCK is a circuit that is used very frequently in the work of hardware engineers. It can be said that as long as the board is not mini, there is a DC-DC in all likelihood. Therefore, understanding and learning about it is a top priority, and it also tests a hardware engineer's mastery of the characteristics and usage of basic components such as MOS tubes, inductors, and capacitors.
This article will explain the DC-DC BUCK topology in detail, and further explain the principles and parameter selection of each part of the actual block diagram of the DCDC chip. The logical inference is mainly based on engineering inference, supplemented by formula calculation, which has learning significance for practical design. .
This article is mainly for knowledge recording and learning sharing, and some pictures are from the Internet.
BUCK principle
The following figure shows the topology of synchronous BUCK:
1. When Q1 is turned on and Q2 is turned off, the voltage at SW terminal is the input voltage VIN. VIN charges the inductor L1, and the inductor current increases. VIN=VL+VOUT. At this time, the inductor voltage is positive on the left and negative on the right. The direction of current flow is the blue loop shown in the figure.
2. When Q1 is turned off and Q2 is turned on, since the inductor current cannot change suddenly, the current forms a loop according to the red line path in the figure below and supplies power to the load. At this time, the inductor current decreases. The inductor voltage is negative on the left and positive on the right.
According to the volt-second law and other derivation, synchronization BUCK derives a more important formula:
VIN*D=VOUT
Simply put, the duty cycle is directly related to the input and output voltage. Relatively speaking, if the output voltage is lower, the duty cycle will be lower. The understanding is that because the output voltage is low, it is necessary to open the upper MOS tube to the inductor. Less time to recharge!
(It should be noted here that this is only a theoretical value measured under perfect conditions. The actual value may be different from the theoretical value due to loss and other circumstances)
According to the topology in the above figure, the waveform in the following figure is obtained
a. When Q1 is turned on, Q2 is turned off, Vsw is high, IQ1 increases, IQ2 is zero, and the inductor current increases.
b'. When Q1 is turned off, Q2 is turned on, Vsw is low, IQ1 is zero, IQ2 decreases, and the inductor current decreases.
c. Throughout the steady-state process, the inductor current continues to increase and decrease.
d. We often call the opening time of the upper tube Ton, and the closing time Toff. The sum of the two is a period.
Here is an interesting simulation waveform. The green color is the SW voltage signal at the left end of the inductor, and the red color is the output voltage signal.
When there is no output capacitor but there is a load, you can see the fluctuation of the output voltage as the SW switch changes. When SW is high, VIN charges the inductor and the output voltage increases; when SW is low, the inductor consumes its own energy. The output voltage becomes low.
DC-DC chip block diagram
The BUCK topology diagram is relatively simple. We will give a more in-depth explanation based on the actual DC-DC chip block diagram.
In the DC-DC chip block diagram, there are still the two MOS tubes, inductor, capacitor, and some more logic circuits such as Driver and Controller.
Simply put, it uses the principle that the inductor stores energy and the current cannot change suddenly. It controls the opening and closing of the high-side MOS and low-side MOS through PWM control of the HS Driver and LS Driver to adjust the output function.
According to functions, it is divided into logic drive, power conversion, load, voltage sampling and feedback compensation.
bootstrap capacitor
describe
CBOOT, also called CBST, means bootstrap capacitor in Chinese.
effect
Keep High-side MOS turned on. (It is crucial to maintain these two words)
work process
1. In the initial state, LS is on, HS is off (the PWM input of HS is low), the SW voltage is 0V, and VCC charges CBST to the VCC voltage through the diode (red path).
2. When PWM is high and the HG voltage rises, HS begins to conduct and the SW voltage rises. Due to the voltage difference between CBST and CBST, the voltage of BST will be raised simultaneously, and HG and BST are connected inside the driver, and the HG voltage will also increase. It will follow the rise of BST (blue current path), thereby maintaining the voltage difference between HG-SW high enough to keep HS on.
Selection
The most common is 0.1uF.
1. The bootstrap capacitor cannot be too small, at least it must be greater than the conduction energy required by the high-side MOS + leakage current + high-side driver current consumption + leakage current of the bootstrap capacitor itself.
2. The bootstrap capacitor cannot be too large. If it is too large, when charging the bootstrap capacitor, the bootstrap capacitor cannot be fully charged within this cycle, resulting in a small upper voltage, failure to turn on the high-side MOS, and abnormal output.
From a design perspective, the withstand voltage needs to exceed the VCC voltage inside the chip, which is the LDO output voltage inside the DCDC chip, and is commonly 3.3V. There are also chips that do not have LDO inside and require external access to VCC.
Output inductor
DCR, this is the DC resistance of the inductor. The smaller the value, the less loss in the inductor. However, some chips will use the DCR of the inductor for current detection. If this function is available, the smaller the value, the better.
Interestingly, if the DCR is relatively large, this part of the loss will be expressed in the form of an increase in the inductor temperature, which will reduce the inductance value of the inductor and increase the ripple current and ripple voltage.
Saturation current usually refers to the DC current corresponding to when the inductance drops by 30%.
Temperature rise current usually refers to the current value when the inductor heats up by 40 degrees.
Logically, the inductance has a minimum value, and it must be greater than a certain value to be able to accommodate the ripple current.
According to the characteristics of the inductor, the larger the inductor, the stronger the energy storage capacity and the more obvious the suppression effect on the current, so the ripple will be smaller, but the dynamic response will be reduced. At the same time, generally speaking, the larger the inductor, the larger the size, the larger the DCR, and the loss of the inductor increases.
The current flowing through the inductor is composed of an AC component and a DC component. The frequency of the AC component is the same as the switching frequency, and will flow to the ground through the capacitor, resulting in a response output ripple voltage related to ESR.
When selecting an inductor, make sure that the saturation current Isat is greater than the inductor current peak value Ipeak to avoid inductor saturation and damage to the MOS and inductor caused by a drop in inductance value.
Where r is the current ripple rate, generally selected around 0.3~0.5.
working frequency
Increasing the frequency will shorten the time of one cycle and the ripple current will decrease.
Output Capacitance and Ripple
This is still the waveform diagram, without output capacitor and with load. To simply understand, the root cause of power supply ripple is the fluctuation of the inductor current during the switching process of the MOS tube, which further leads to the fluctuation of the output voltage.
effect:
Energy storage, filtering out power supply noise
Selection:
Withstand voltage, capacitance, ESR and other parameters.
The withstand voltage generally needs to be derated by 80%;
Theoretically, the larger the capacitance, the better the effect. However, different capacitors have different impedances at the same frequency, as shown in the figure below. Capacitors are generally mixed and matched, that is, a combination of large-capacitance solid electrolytic capacitors and small-capacitance MLCCs to achieve low impedance across the entire frequency range.
When other parameters are the same, the smaller the ESR of the output capacitor, the smaller the output ripple will be. From the perspective of engineering applications, the output has ripple current. The larger the ESR, the larger the voltage change in the capacitor, which is part of the ripple.
Feedforward capacitor
The feedforward capacitor, C7 in the figure below, is connected in parallel to the upper end of the FB voltage dividing resistor.
The function mechanism of the feedforward capacitor is to use the principle that the voltage across the capacitor cannot mutate, and feedback the weak changes in VOUT to the FB pin of the chip in a timely and rapid manner. Therefore, its purpose is to increase the transient response of the chip and optimize the ripple.
loss
switching losses
Switching losses are mainly in high-side MOS. During the process of turning on and off, there is an overlap area of voltage and current. At this time, the power consumption is:
In other words, it takes time to open the MOS tube. Although this process is very fast according to our common understanding, it cannot be ignored in engineering.
The higher the switching frequency, the more conversions occur in the same time period, so switching frequency is directly proportional to switching losses.
As for the lower MOS, this is a bit interesting. You need to go through the process. First, the upper MOS is turned on to charge the inductor, and then the upper MOS is turned off and enters the dead time. At this time, the body diode of the lower MOS tube performs freewheeling. Dead time After the time is over, the lower MOS tube is turned on. Since the VDS voltage is very low during the opening process of the lower MOS tube, it can be considered that the switching loss of the lower MOS tube is very small.
conduction loss
There will be conduction loss when the upper and lower MOS are turned on. This parameter is related to Rdson, because the MOS does not have absolutely zero resistance when it is turned on. As long as there is resistance and current flows, there will be consumption.
It should be noted here that in the steady-state continuous conduction mode, the amount of inductor charging current and discharge current is the same, so the passing current of the upper and lower tubes is the same, so the HS and LS conduction loss ratio is related to the PWM duty cycle. If the duty cycle D is 50%, it can be considered that the conduction losses of the upper and lower tubes are the same.
But most D is less than 50%, so we say that the conduction loss of the down tube is greater than that of the upper tube. At the same time, the upper tube is mainly a switching loss.
dead time
In order to prevent the upper and lower MOS from turning on at the same time and short-circuiting VCC to ground, there is a dead time between the two MOS switches. The lower tube is turned off and after the dead time passes, the upper tube is turned on again. At this time, the body diode of the lower tube has losses caused by freewheeling during the dead time and losses caused by reverse recovery.
The body diode has conduction voltage drop and current, which will cause losses:
There is also reverse recovery loss:
Inductance loss
a. Coil loss
Produced by the inductor DC resistance DCR, the output current passes through DCR, and the loss is expressed in the form of heat.
Coil loss can be calculated using the following formula:
b. Core loss
Core loss is related to the core material and is difficult to calculate. You need to contact the inductor manufacturer to obtain it. Generally speaking, the higher the frequency, the greater the magnetic loss.
Loss summary
I found a better picture online.
The switching loss is related to the switching frequency and gate charge Qg, while the conduction loss is related to Rdson.
Generally speaking
High Side MOS has large switching loss and small conduction loss
Low Side MOS has small switching loss and large conduction loss.
Summarize
After thorough research on the DC-DC BUCK circuit, I found it to be very interesting. At first I saw the mountains as mountains, then I saw the mountains as not mountains, and finally I saw the mountains as mountains again. The same thing gives me completely different feelings.